A CMOS Channel-Select Tunable Filter for 3G Wireless Receivers

1
A CMOS Channel-Select Tunable Filter for 3G
Wireless Receivers
by Hussain Alzaher, Noman Tasadduq1
andMohammed Ismail21. Electrical Engineering
Department, KFUPM, Dhahran 31261, Saudi Arabia2.
Analog VLSI Lab., Ohio-State University, Columbus
43210, USA
2
Outline

• Introduction
• 2G standards
• Evolution of 3G standards
• Receiver Architectures
• Superheterodyne
• Double IF conversion
• Direct conversion
• 3G multi-standards
• Analog - Digital Interface
• Baseband Design Requirements
• Proposed Baseband Filter Techniques
• Motivations and literature review
• DCCF based technique
• Proposed filter
• Design
• Experimental Results

3
Introduction

• Second-generation (2G) mobile radio systems
• Global System for Mobile Communications (GSM) in
  Europe and worldwide
• North American Digital Cellular (IS-54/IS-136)
  (IS-95) in USA
• Personal Digital Cellular (PDC) in Japan
• Different Characteristics Frequency band,
  Channelization, Frame size Bit Rate
• Different Bandwidths PDC (13KHZ), IS-54 (15KHz),
  GSM (100KHz) IS-95 (630KHz)
• Limited to Voice and Low Data-rate

4
Introduction

• Third generation (3G) Future wireless systems
• Broadband Multimedia and High Data Rate
• Universal Access and Global Roaming
• Wide-band Code Division Multiple Access (WCDMA)
• More Bandwidth 2.1/4/8 MHz for Different data
  rate
• Backward Compatibility to 2G Saving Today's
  Investment
• Multi-standard Wireless Receivers

5
Introduction

• 2G digital cellular systems

6
Introduction

• System characteristics of 3G standards

7
Receiver Architectures

• 3G Receiver
• Low-cost Single-chip Low power
  Multi-standard
• Conventional Superheterodyne Receiver
• Not Suitable Discrete-component Filters and
  Expensive Technologies
• Direct Conversion wide-band IF double
  conversion
• Integrated Architectures
• Eliminate Off-chip Filtering
• Perform Channel Filtering at Baseband
• Allow Design of Programmable Multi-standard
  Integrated Channel Select Filter
• Adjacent Channel Blocker Require High Dynamic
  Range Designs

8
Receiver Architectures
Conventional superheterodyne receiver
9
Receiver Architectures
Wide-band IF with double conversion receiver
10
Receiver Architectures
Direct conversion receiver
11
Receiver Architectures
A typical architecture for a multi-standard
receiver
12
Receiver Architectures

• Sharing Filter Low power Cost-effective
• Most Significant Hardware Saving
• Digital Tuning Eliminates Auxiliary DAC
• Digital Automatic Frequency Tuning
• Programmable DR Challenge

13
Analog - Digital Interface

• Digital Filtering ADC Design Stringent
• Hard Implementation More Power
• Aliasing considerations
• High order filters ADCs with low dynamic range
  and sampling rate
• Analog filter Much less power
• A 16-bit 20MHz 183mA
• A 6-bit 40MHz ADC 23mA

14
Baseband Design Requirements

• Attenuate blockers
• Highly Linear Inter-modulation (IP3)
• Low Noise
• High Dynamic Range

15
Motivations and Literature Review
Proposed Baseband Filter Techniques

• gm-C Filters Poor Dynamic Range
• S-C Filters Frequency vs. Power
• Active-RC and gm-RC Capacitor Matrices
• Power Area Cutoff Frequency Precision
• Interleaving Filtering/Amplification Improving
  Dynamic Range

16
Proposed Baseband Filter Techniques

• Multi-standard Requirement
• Wide Programmability for Different Standard
• PDC, IS-54, GSM, IS-95, WCDMA
• Precise Frequency for Channel Selection
• S-C Filter Problem with 2.1MHz WCDMA
• Active RC and Highly linear gm-RC Optimizing
  Power
• Capacitor Matrices Large Area for Low Frequency
  Precision

17
Proposed Baseband Filter Techniques

• Multi-standard performance comparison

18
DCCF Based Technique
Proposed Baseband Filter Techniques

• Digitally controlled current follower (DCCF)
  unity gain voltage buffer
• Poly-silicon resistors and capacitors
• Current division network (CDN)

19
DCCF Based Technique
Digitally controlled current follower (DCCF)
20
DCCF Based Technique
21
DCCF Based Technique
Original Buffer
22
DCCF Based Technique
Transformation
23
DCCF Based Technique
Improved buffer
24
DCCF Based Technique
Fully Differential Architecture
Fully differential building block topology
25
DCCF Based Technique
Fully differential realization of the proposed
DCCF-VB
26
Filter Design

• Adding R-2R Ladders to Filter Design
• Allow the accommodation of GSM, IS-54 with 15Khz,
  100Khz Bandwidths
• GSM R10kW, C160pF
• IS-54 R10kW, C1nF
• IS-54 8-bit R2R ladders R10kW, C4pF

27
Filter Design
where
28
Filter Design
Proposed second-order filter section
29
Filter Design
30
Experimental Results
Photomicrograph of the 6-th order filter
31
Experimental Results
Measured ac response PDC and IS-54
32
Experimental Results
Measured ac response GSM
33
Experimental Results
Measured ac response IS-95
34
Experimental Results
Measured ac response WCDMA
35
Experimental Results
Performance of proposed filter based on DCCF