Title: FINITE STATE MACHINES  II
1FINITE STATE MACHINES  II
 STATE MINIMIZATION
 PARTITIONING MINIMIZATION PROCEDURE
 VENDING MACHINE EXAMPLE
 ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
 PROCEDURE
 EXAMPLE
 ALGORITHMIC STATE MACHINES (ASM) CHARTS
 COMPLETE FSM DESIGN EXAMPLE
 PARALLELTOSERIAL CONVERTER WITH PARITY GENERATOR
__________________________________________________
ECSE323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
2FINITE STATE MACHINES  II
 STATE MINIMIZATION
 PARTITIONING MINIMIZATION PROCEDURE
 DEFINITION Two states Si and Sj are said to be
equivalent if and only if for every input
sequence , the same output sequence will be
produced regardless of whether Si or Sj are the
initial states.  DEFINITION OF 1SUCCESSOR If the machine moves
from state Si to state Sv when input w 1, then
we say that Sv is a 1successor of Si  DEFINITION OF 0SUCCESSOR If the machine moves
from state Sj to state Su when input w 0, then
we say that Su is a 0successor of Si  IF STATES Si AND Sj ARE EQUIVALENT, THEN THEIR
 CORRESPONDING KSUCCESSORS (FOR ALL K) ARE ALSO
 EQUIVALENT.
__________________________________________________
ECSE323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
3FINITE STATE MACHINES  II
 STATE MINIMIZATION
 PARTITIONING MINIMIZATION PROCEDURE (CONTINUES)
 DEFINITION A PARTITION CONSISTS OF ONE OR MORE
BLOCKS, WHERE EACH BLOCK COMPRISES A SUBSET OF
STATES THAT MAY BE EQUIVALENT, BUT THE STATES IN
A GIVEN BLOCK ARE DEFINITELY NOT EQUVALENT TO THE
STATES IN THE OTHER BLOCK.
__________________________________________________
ECSE323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
4FINITE STATE MACHINES  II
 STATE MINIMIZATION
 PARTITIONING MINIMIZATION PROCEDURE (CONTINUES)
 PROCEDURE
 1) ALL STATES BELONG TO THE INITIAL PARTITION P1
 2) P1 IS PARTITIONED IN BLOCKS SUCH THAT THE
STATES IN EACH BLOCK GENERATE THE SAME
OUTPUT.  3) CONTINUE TO PERFORM NEW PARTITIONS BY TESTING
WHETHER THE KSUCCESSORS OF THE STATES IN EACH
BLOCK ARE CONTAINED IN ONE BLOCK. THOSE STATES
WHOSE KSUCCESSORS ARE IN DIFFERENT BLOCKS
CANNOT BE IN ONE BLOCK.  4) PRCEDURE ENDS WHEN A NEW PARTITION IS THE SAME
AS .THE PREVIOUS PARTITION
5FINITE STATE MACHINES  II
 STATE MINIMIZATION
 PARTITIONING MINIMIZATION PROCEDURE (CONTINUES)
 EXAMPLE Consider the following state transition
table 
 P1 (ABCDEFG)
 P2 (ABD)(CEFG) Diff. Outputs.
 Because (CEFG) 0successors are (FFEF) in
same block,  (CEFG) 1successors are (ECDG)
in diff. block,  F must be different from C, E and G
 P3 (ABD)(CEG)(F)
 P4 (AD)(B)(CEG)(F)
 Same process for (AD) and (CEG) gives
 P5 (AD)(B)(CEG)(F)
 P5 P4
6FINITE STATE MACHINES  II
 STATE MINIMIZATION
 PARTITIONING MINIMIZATION PROCEDURE (CONTINUES)
 EXAMPLE (CONTINUES) MINIMAL STATE TRAMSITION
TABLE  ORIGINAL TABLE
 P4
(AD)(B)(CEG)(F) 
MINIMIZED TABLE
7FINITE STATE MACHINES  II
 STATE MINIMIZATION
 VENDING MACHINE EXAMPLE
 Design an FSM that will dispense candy under the
following  conditions
 1. The machine accepts nickels and dimes
 2. 15 cents releases a candy from the machine
 3. If 20 cents is deposited, the machine will
not return the change, but it credit the buyer
with 5 cents and wait for the buyer to make a
second purchase
__________________________________________________
ECSE323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
8FINITE STATE MACHINES  II
 STATE MINIMIZATION
 VENDING MACHINE EXAMPLE (Continues)
__________________________________________________
ECSE323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
9FINITE STATE MACHINES  II
 STATE MINIMIZATION
 VENDING MACHINE EXAMPLE (Continues)
__________________________________________________
ECSE323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
10FINITE STATE MACHINES  II
 STATE MINIMIZATION VENDING MACHINE EXAMPLE
(Continues)
__________________________________________________
ECSE323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
11FINITE STATE MACHINES  II
 STATE MINIMIZATION
 VENDING MACHINE EXAMPLE (Continues)
 P1 (S1, S2, S3,
S4, S5, S6, S7, S8, S9)  P2
(S1, S2, S3, S6)(S4, S5, S7, S8, S9) 
P3 (S1)(S3)(S2, S6)(S4, S5, S7, S8, S9) 
P4 (S1)(S3)(S2, S6)(S4, S7, S8)(S5,S9) 
P5 (S1)(S3)(S2, S6)(S4, S7, S8)(S5,S9)
__________________________________________________
ECSE323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
12FINITE STATE MACHINES  II
 STATE MINIMIZATION VENDING MACHINE EXAMPLE
(Continues)  MINIMIZED STATE TRANSITION TABLE AND DIAGRAM
13FINITE STATE MACHINES  II
 STATE MINIMIZATION VENDING MACHINE
EXAMPLE (Continues)  MINIMIZED STATE TRANSITION DIAGRAM Mooretype
versus Mealytype  MOORETYPE
MEALY_TYPE
14FINITE STATE MACHINES  II
 ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
 PROCEDURE is the reverse of the synthesis
process.  1. OUTPUTS OF FLIPFLOPS ARE THE INTERNAL
STATES.  2. INPUT EQUATIONS TO FLIPFLOPS DETERMINE
NEXT INTERNAL  STATE.
 3. EXCITATION TABLE IS CONSTRUCTED FROM THESE
INPUT  EQUATIONS TO FLIPFLOPS. OUTPUT
EQUATIONS ARE PRODUCED.  4. THE STATEASSIGNED TABLE IS PRODUCED FROM
THE EXCITATION TABLE  5. THE STATETRANSITION TABLE IS PRODUCED BY
ASSIGNING A STATE  IDENTIFICATION LETTER TO EACH ASSIGNED
STATE.  6. THE STATETRANSITION DIAGRAM IS PRODUCED
FROM THE STATE  TRANSITION TABLE.
__________________________________________________
ECSE323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
15FINITE STATE MACHINES  II
 ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
 EXAMPLE ANALYZE THE FOLLOWING CIRCUIT
 Exitation equations DY1 w !y1 w y2

DY2 w y1 w y2 
z y1 y2  Next state
equations 
Y1 DY1 w !y1 w y2 
Y2 DY2 w y1 w y2
__________________________________________________
ECSE323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
16FINITE STATE MACHINES  II
 ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
EXAMPLE (Continues)
Exitation equations
DY1 w !y1 wy2 DY2
w y1 w y2 z
y1 y2 Next state equations
Y1 DY1 w !y1 w y2
Y2 DY2 w y1 w y2
__________________________________________________
ECSE323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
17FINITE STATE MACHINES  II
 ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
EXAMPLE (Continues)
__________________________________________________
ECSE323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
18FINITE STATE MACHINES  II
 ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
ANOTHER EXAMPLE Analyze the following circuit
__________________________________________________
ECSE323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
19FINITE STATE MACHINES  II
 ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
ANOTHER EXAMPLE (Continues)

Excitation Equations 
J1 w 
K1 !w !y2 
J2 w y1 
K2 !w  z y1 y2

__________________________________________________
ECSE323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
20FINITE STATE MACHINES  II
 ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
ANOTHER EXAMPLE (Continues)
 Excitation Equations
 J1 w
 K1 !w !y2
 J2 w y1
 K2 !w
 z y1 y2


__________________________________________________
ECSE323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
21FINITE STATE MACHINES  II
 ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
ANOTHER EXAMPLE (Continues)  EXCITATION TABLE
STATEASSIGNED TABLE 
__________________________________________________
ECSE323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
22FINITE STATE MACHINES  II
 ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS
EXAMPLE (Continues)
__________________________________________________
ECSE323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
23FINITE STATE MACHINES  II
 ALGORITHMIC STATE MACHINES (ASM) CHARTS
 DEFINITION An ASM is a type of flowchart that
can be used to represent the state transitions
and generated outputs for LARGE FSMs.  THREE TYPES OF ELEMENTS
 STATE BOX, DECISION BOX, CONDITIONAL OUTPUT BOX.
__________________________________________________
ECSE323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
24FINITE STATE MACHINES  II
 ALGORITHMIC STATE MACHINES (ASM) CHARTS
(Continues)  Example Mooretype
__________________________________________________
ECSE323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
25FINITE STATE MACHINES  II
 ALGORITHMIC STATE MACHINES (ASM) CHARTS
(Continues)  EXAMPLE (Mealytype)
__________________________________________________
ECSE323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
26FINITE STATE MACHINES  II
 ALGORITHMIC STATE MACHINES
(ASM) CHARTS (Continues)  ANOTHER EXAMPLE (ARBITER MOORETYPE FSM) FSM
THAT CONTROLS THE ACCESS BY VARIOUS DEVICES TO A
SHARED  RESOURCE IN A GIVEN SYSTEM. ONLY ONE DEVICE CAN
USE THE RESOURCE AT A TIME.
27FINITE STATE MACHINES  II
 COMPLETE FSM DESIGN EXAMPLE
 PARALLELTOSERIAL CONVERTER WITH PARITY
GENERATOR  Word description
 Design a digital systems that will convert an
8bit parallel message, (b7 , b6 , b5 , b4 , b3
, b2 , b1 , b0), composed of 7bit ASCII
character plus an initially set to 0 parity bit,
into an 8bit serial message with the correct
parity bit set into bit b7 .
__________________________________________________
ECSE323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
28FINITE STATE MACHINES  II
 COMPLETE FSM DESIGN EXAMPLE
 PARALLELTOSERIAL CONVERTER WITH PARITY
GENERATOR  BLOCK DIAGRAM (Data Path and Control Unit)
__________________________________________________
ECSE323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
29FINITE STATE MACHINES  II
 COMPLETE FSM DESIGN EXAMPLE
 PARALLELTOSERIAL CONVERTER WITH PARITY
GENERATOR  STATE TRANSITION TABLE
__________________________________________________
ECSE323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
30FINITE STATE MACHINES  II
 COMPLETE FSM DESIGN EXAMPLE
 PARALLELTOSERIAL CONVERTER WITH PARITY
GENERATOR  STATEASSIGNED TABLE
 CHOICE OF FLIPFLOPS AND EXCITATION EQUATION
 Dy Y w ? y
__________________________________________________
ECSE323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.
31FINITE STATE MACHINES  II
 COMPLETE FSM DESIGN EXAMPLE
 PARALLELTOSERIAL CONVERTER WITH PARITY
GENERATOR  CIRCUIT
__________________________________________________
ECSE323/Department of Electrical and Computer
Engineering/McGill University/ Prof.
Marin. Figures taken from Fundamentals of Digital
Logic with VHDL Design, S. Brown and Z. Vranesic,
2nd Edition, McGraw Hill.