ELEC 5270-001/6270-001 (Fall 2006) Low-Power Design of Electronic Circuits (ELEC 5970/6970) Low Voltage Low Power Devices - PowerPoint PPT Presentation

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ELEC 5270-001/6270-001 (Fall 2006) Low-Power Design of Electronic Circuits (ELEC 5970/6970) Low Voltage Low Power Devices

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ELEC 5270-001/6270-001 (Fall 2006) Low-Power Design of Electronic Circuits (ELEC 5970/6970) Low Voltage Low Power Devices Vishwani D. Agrawal James J. Danaher Professor – PowerPoint PPT presentation

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Title: ELEC 5270-001/6270-001 (Fall 2006) Low-Power Design of Electronic Circuits (ELEC 5970/6970) Low Voltage Low Power Devices


1
ELEC 5270-001/6270-001 (Fall 2006)Low-Power
Design of Electronic Circuits(ELEC 5970/6970)
Low Voltage Low Power Devices
  • Vishwani D. Agrawal
  • James J. Danaher Professor
  • Department of Electrical and Computer Engineering
  • Auburn University
  • http//www.eng.auburn.edu/vagrawal
  • vagrawal_at_eng.auburn.edu

2
Capacitances
VDD
C1
In
Out
C2
CW
GND
3
Miller Capacitance
VDD
C1
In
Out
CM
C2
CW
GND
4
Before Transition
VDD
C1
VDD
0
In
Out
CM
C2
CW
GND
5
After Transition
VDD
Energy from supply 2 CM VDD2 Effective
capacitance 2 CM
from pullup devices of previous gate
C1
-VDD
0
In
Out
CM
C2
CW
GND
6
Capacitances in MOSFET
Cgd
Cgs
Gate
Gate oxide
Source
Drain
Cg
Cs
Cd
Bulk
7
Bulk nMOSFET
Polysilicon
Gate
Drain
W
Source
n
n
L
p-type body (bulk)
SiO2 Thickness tox
8
Gate Capacitance
Cg Cox WL C0, intrinsic cap. Cg
Cpermicron W eox Cpermicron Cox L --
L tox where eox 3.9e0 for Silicon
dioxide 3.98.8510-14 F/cm
9
Intrinsic Capacitances
Capacitance Region of operation Region of operation Region of operation
Capacitance Cutoff Linear Saturation
Cgb C0 0 0
Cgs 0 C0 /2 2/3 C0
Cgd 0 C0 /2 0
Cg CgsCgdCgb C0 C0 2/3 C0
Weste and Harris, CMOS VLSI Design,
Addison-Wesley, 2005, p. 78.
10
Low-Power Transistors
  • Device scaling to reduce capacitance and voltage.
  • Body bias to reduce threshold voltage and
    leakage.
  • Multiple threshold CMOS (MTCMOS).
  • Silicon on insulator (SOI)

11
Device Scaling
  • Reduced dimensions
  • Reduce supply voltage
  • Reduce capacitances
  • Reduce delay
  • Increase leakage due to reduced VDD / Vth

12
A Simplistic View
  • Assume
  • Dynamic power dominates
  • Power reduces as square of supply voltage should
    reduce with device scaling
  • Power reduced linearly with capacitance should
    reduce with device scaling
  • Delay is proportional to RC time constant R is
    constant with scaling, RC should reduce
  • Power reduces with scaling

13
Simplistic View (Continued)
  • What if voltage is further reduced below the
    constant electric field value?
  • Will power continue to reduce? Yes.
  • Since RC is independent of voltage, can clock
    rate remain unchanged?
  • Answer to last question
  • Yes, if threshold voltage was zero.
  • No, in reality. Because higher threshold voltage
    will delay the beginning of capacitor
    charging/discharging.

14
Consider Delay of Inverter
VDD
R
In
Out
C
t B
t B
Charging of C begins
GND
15
Idealized Input and Output
t f
VDD
Vth
INPUT
0.5VDD
t B t f Vth /VDD
Gate delay
0.5VDD
OUTPUT
time
t B
0.69CR
16
Gate Delay
For VDD gtVth Gate delay (t fVth/VDD) 0.69RC
0.5 t f t f (Vth/VDD 0.5 ) 0.69RC For
VDD Vth Gate delay 8
17
Approx. Gate Delay vs. VDD
Gate delay
0.5t f
0.69RC
0.5t f
0 1 2 3 4 5
VDD /Vth
18
Power - Delay vs. VDD
Gate delay
0.5t f
Power
0.69RC
With leakage
0.5t f
0 1 2 3 4 5
VDD /Vth
19
Optimum Threshold Voltage
Vth 0.7V Vth 0.3V
Delay
Delay or Energy-delay product
Energy-delay product
0 1 2 3 4 5 6
VDD / Vth
20
Bulk nMOSFET
Polysilicon
Vgs
Vgd
Gate
Drain
W
Source
n
n
L
p-type body (bulk)
SiO2 Thickness tox
21
Transistor in Cut-Off State
Polysilicon gate SiO2 p-type body

- - - - - - - - - - - - - - - - - -
-


Vg lt 0
22
Threshold Voltage, Vth
Polysilicon gate SiO2 p-type body


-
Depletion region
0 lt Vg lt Vth


Vth is a function of Dopant concentration, Thickn
ess of oxide
Polysilicon gate SiO2 p-type body


-
  • - - - - - - - - - - - - - - - - - -
  • Depletion region

Vg gt Vth
23
a-Power Law Model
Vgs gt Vth and Vds gt Vdsat Vgs Vth (Saturation
region) ß Ids Pc - (Vgs
Vth)a 2 where ß µCoxW/L, µ
mobility For fully ON transistor, Vgs Vds
VDD ß Idsat Pc - (VDD Vth)a
2 T. Sakurai and A. R. Newton, Alpha-Power
Law MOSFET Model and Its Applications to CMOS
Inverter Delay and Other Formulas, IEEE J. Solid
State Circuits, vol. 25, no. 2, pp. 584-594, 1990.
24
a-Power Law Model (Cont.)
400 300 200 100 0
Shockley a-power law Simulation
Ids (µA)
Idsat
Vgs 1.8V
0 0.3 0.6 0.9 1.2
1.5 1.8
Vds
25
a-Power Law Model (Cont.)
0 Vgs lt Vth cutoff Ids IdsatVds/Vdsat Vd
s lt Vdsat linear Idsat Vds gt
Vdsat saturation Vdsat Pv (Vgs Vth)a/2
26
a-Power Law Model (Cont.)
  • a 2, for long channel devices or low VDD
  • a 1, for short channel devices

27
Power and Delay
Power CVDD2 CVDD 1 1 Inverter
delay ---- (--- --- ) 4 Idsatn
Idsatp KVDD ------- (VDD
Vth)a
28
Power-Delay Product
VDD3 Power Delay constant
------- (VDD Vth)a
Power Delay
0.6V 1.8V 3.0V VDD
29
Optimum Threshold Voltage
For minimum power-delay product
3Vth VDD --- 3 a For long channel
devices, a 2, VDD 3Vth For very short
channel devices, a 1, VDD 1.5Vth
30
Leakage
VDD
IG
Ground
R
n
n
Isub
IPT
ID
IGIDL
31
Leakage Current Components
  • Subthreshold conduction, Isub
  • Reverse bias pn junction conduction, ID
  • Gate induced drain leakage, IGIDL due to
    tunneling at the gate-drain overlap
  • Drain source punchthrough, IPT due to short
    channel and high drain-source voltage
  • Gate tunneling, IG through thin oxide

32
Subthreshold Leakage
Vgs Vth Isub I0 exp( ----- ) nvth
Ids 1mA 100µA 10µA 1µA 100nA 10nA 1nA 100pA 10pA
Saturation region
Subthreshold region
Vth
0 0.3 0.6 0.9 1.2 1.5 1.8
V Vgs
33
Normal CMOS Inverter
VDD
o
output
input
GND
SiO2
Polysilicon (input)
output
VDD
GND
metal 1
p
n
p
p
n
n
n-well
p-substrate (bulk)
34
Leakage Reduction by Body Bias
VBBp VDD
o
output
input
GND VBBn
SiO2
Polysilicon (input)
VBBn
VBBp
VDD
output
GND
metal 1
p
n
p
p
n
n
n-well
p-substrate (bulk)
35
Body Bias, VBBn
Polysilicon gate SiO2 p-type body


-
Depletion region
0 lt Vg lt Vth


Vt is a function of Dopant concentration, Thickne
ss of oxide
Polysilicon gate SiO2 p-type body

- - - - - - - - - - - - - - - - - -
-



Vg lt 0
36
Further on Body Bias
  • Large body bias can increase gate leakage (IG)
    via tunneling through oxide.
  • Body bias is kept less than 0.5V.
  • For VDD 1.8V
  • VBBn - 0.4V
  • VBBp 2.2V

37
Summary
  • Device scaling down reduces supply voltage
  • Reduced power
  • Increases delay
  • Optimum power-delay product by scaling down
    threshold voltage
  • Threshold voltage reduction increases
    subthreshold leakage power
  • Use body bias to reduce subthreshold leakage
  • Body bias may increase gate leakage
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