ITRS Design System Drivers July, 2010 Design ITWG Juan-Antonio Carballo Tamotsu Hiwatashi William Joyner Andrew Kahng Noel Menezes Shireesh Verma - PowerPoint PPT Presentation

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ITRS Design System Drivers July, 2010 Design ITWG Juan-Antonio Carballo Tamotsu Hiwatashi William Joyner Andrew Kahng Noel Menezes Shireesh Verma

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ITRS Design + System Drivers July, 2010 Design ITWG Juan-Antonio Carballo Tamotsu Hiwatashi William Joyner Andrew Kahng Noel Menezes Shireesh Verma – PowerPoint PPT presentation

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Title: ITRS Design System Drivers July, 2010 Design ITWG Juan-Antonio Carballo Tamotsu Hiwatashi William Joyner Andrew Kahng Noel Menezes Shireesh Verma


1
ITRS Design System DriversJuly, 2010Design
ITWG Juan-Antonio CarballoTamotsu Hiwatashi
William Joyner Andrew Kahng Noel Menezes
Shireesh Verma
2
Overview (2004-Today)1. Increasingly
quantitative roadmap2. Increasingly complete
driver set
2010
2009
MTM RFAMS Driver Updated Consumer, MPU,
and Networking Drivers Power roadmap
chart Upgraded RFAMS section
2008
MTM extension iNEMI synch SW !!
MTM extension iNEMI SW !!
2007
More Than Moore (MTM) analysis iNEMI
Updated Consumer Stationary, Portable
architecture, and Networking Drivers
2006
Updated Consumer Stationary, Portable, and
Networking Drivers
2005
Consumer Stationary, Portable, Networking
Drivers
Consumer Stationary, Portable Drivers
2004
Consumer Portable Driver
Additional Design Metrics DFM Extension System
level extension
Driver study
System Drivers Chapter
Revised Design Metrics DFM extension
Revised Design Technology Metrics
Revised Design metrics
Design Technology metrics
Explore Design metrics
Design Chapter
3
Selected Messages 2010
  • Design productivity continues to be center focus
    of design technology roadmap, as scaling depends
    on time to market
  • Accurate design productivity and cost models are
    key
  • Power consumption has become the key technical
    parameter that controls feasible semiconductor
    scaling
  • Power-driven device roadmap, frequency pushed to
    flat trend
  • More Than Moore has become a necessary component
    of semiconductor product scaling
  • Mixed SiP-SoC analog-digital drivers need to be
    roadmapped

4
Design / System Drivers 2010-2011 Plans
  • Design chapter
  • Improvement of design productivity and cost
    models
  • Develop Power Chart based on STRJ
    productivity chart
  • Ensure 3D / TSV content consistent with other
    chapters
  • Improve DFM section, including Design for
    reliability rows
  • Overhaul of Verification , L/C/P sections
  • System Drivers chapter
  • Update MPU frequency roadmap (flat trend),
    evaluate impact
  • Update of SOC-CP and SOC-CS models (driven from
    TWGs)
  • Update AMS/RF Driver / fabric with Wireless TWG
  • More-Than-Moore RFAMS driver SiP-SoC (based on
    SoC-P)
  • Other Cross-TWG and public activity
  • PIDS increase design-driven requirements
    definition
  • 3D/TSV hold for ACTION
  • Continue other key interactions AP,
    Interconnect, Test
  • Incorporate input from 2nd EDA Roadmap Workshop
    (_at_DAC)

5
Design / System Drivers 2010-2011 Plans
  • Design chapter
  • Improvement of design productivity and cost
    models
  • Develop Power Chart based on STRJ
    productivity chart
  • Ensure 3D / TSV content consistent with other
    chapters
  • Improve DFM section, including Design for
    reliability rows
  • Overhaul of Verification , L/C/P sections
  • System Drivers chapter
  • Update MPU frequency roadmap (flat trend),
    evaluate impact
  • Update of SOC-CP and SOC-CS models (driven from
    TWGs)
  • Update AMS/RF Driver / fabric with Wireless TWG
  • More-Than-Moore RFAMS driver SiP-SoC (based on
    SoC-P)
  • Other Cross-TWG and public activity
  • PIDS increase design-driven requirements
    definition
  • 3D/TSV hold for ACTION
  • Continue other key interactions AP,
    Interconnect, Test
  • Incorporate input from 2nd EDA Roadmap Workshop
    (_at_DAC)

6
ITRS Design Productivity RoadmapModel for
upcoming Power Management Roadmap
RTL Functional Verif. Tool Suite
System Design Automation
Transaction Level Modeling
IC Implementation Tool Set
AMP Parallel Processing
Executable Specification
SMP Parallel Processing
Many Core Devel. Tools
Very large block reuse
Transactional Memory
Intelligent Testbench
Source ITRS
7
ITRS Design Productivity RoadmapModel for
upcoming Power Management Roadmap
Design Productivity INNOVATIONS
RTL Functional Verif. Tool Suite
System Design Automation
Transaction Level Modeling
IC Implementation Tool Set
AMP Parallel Processing
Executable Specification
SMP Parallel Processing
Many Core Devel. Tools
Very large block reuse
Transactional Memory
Intelligent Testbench
Design Cost
Source ITRS
8
ITRS Design Productivity RoadmapExpected
upcoming Power Management Roadmap
Design for Power INNOVATIONS
RTL Functional Verif. Tool Suite
System Design Automation
Transaction Level Modeling
IC Implementation Tool Set
AMP Parallel Processing
Executable Specification
SMP Parallel Processing
Many Core Devel. Tools
Very large block reuse
Transactional Memory
Intelligent Testbench
Power Efficiency
Source ITRS
9
SOC Modeling by Japan STRJ-WG1
10
Design / System Drivers 2010-2011 Plans
  • Design chapter
  • Improvement of design productivity and cost
    models
  • Develop Power Chart based on STRJ
    productivity chart
  • Ensure 3D / TSV content consistent with other
    chapters
  • Improve DFM section, including Design for
    reliability rows
  • Overhaul of Verification , L/C/P sections
  • System Drivers chapter
  • Update MPU frequency roadmap (flat trend),
    evaluate impact
  • Update of SOC-CP and SOC-CS models (driven from
    TWGs)
  • Update AMS/RF Driver / fabric with Wireless TWG
  • More-Than-Moore RFAMS driver SiP-SoC (based on
    SoC-P)
  • Other Cross-TWG and public activity
  • PIDS increase design-driven requirements
    definition
  • 3D/TSV hold for ACTION
  • Continue other key interactions AP,
    Interconnect, Test
  • Incorporate input from 2nd EDA Roadmap Workshop
    (_at_DAC)

11
Design and System DriversITRS-iNEMI Domain Space
iNEMI (emulators)
Market requirements
ITRS (Drivers)
Tech requirements
Chip level
System level
Source ITRS Design/System Drivers TWG
Chairman, Dr. Juan-Antonio Carballo
12
New System Drivers? At the right pace
  • Is SIP a new fabric ?
  • What application is the right driver for (leading
    edge) 3D/TSVs ?

2006
2007
2006
2006
2010?
2010?
2010?
Fabrics
?
MPU
SIP
PE/DSP
Memory
AMS
Markets
Consumer Stationary
Network
Consumer Portable
Office
Medical
Automotive
AD
13
ITRS-iNEMI Domain Space SiP-SoC More-than-Moore
Proposal
Chip level
System level
Market requirements
Portable emulator
Portable consumer driver
Tech requirements
1
2
3
RF/AMS Driver
Update portable driver
Update portable emulator
PA Case Study (SoC v. SiP)
14
An Alternative Driver ? Tuner / Demodulator
h
  • Inclusion of AMS/RF sub-driver from ITRS AMS
    driver

Tuner-demod case Study
Power (SiP)
Power (SoC)
Additional rows for combined analog-digital
model
Equivalent cost (SoC)
Requirement Description
Tuner Resolution, operating freqs, power
ADC/DAC bits, order, power, etc.
Demodulator /FEC decoder Gain-bandwidth, power
Equivalent cost (SiP)
15
SOC Modeling by Japan STRJ-WG1
16
Power-Constrained Frequency Scaling
  • Intrinsic frequency scaling activity scaling ?
    13 per year
  • ? Still exceed 150W in 2015
  • 2009
  • To meet market needs frequency growth limited ?
    8 per year
  • 2010 (expected)
  • To meet market needs / additional constraints ?
    flat YTY trend

Power lt 150W
8 frequency scaling
17
Cross-TWG Interaction Design-PIDS
  • Device speed scaling HiPerf CV/I improves by
    13/year
  • Use headroom for further power savings?
  • Three devices in the ITRS roadmap
  • High Performance (HP) Highest Ion and Ioff,
    lowest CV/I
  • Low Operating Power (LOP) Lowest VDD, medium
    Ion, Ioff and CV/I
  • Low Standby Power (LSTP) Lowest leakage, low
    Ion, high CV/I
  • Design providing guidance as to targeted ratio of
    device characteristics
  • Preferred order of dynamic power LOP lt LSTP ltlt
    HP
  • Preferred order of leakage power LSTP lt LOP ltlt
    HP

Design Group
PIDS Group
INPUT
Ratio of HP LOP LSTP
R1
R2
R3
Parameters
Target design freq.(GHz)
Device CV/I
Device Ioff
FEEDBACK
Application driven
Technology driven
18
Design / System Drivers 2010-2011 Plans
  • Design chapter
  • Improvement of design productivity and cost
    models
  • Develop Power Chart based on STRJ
    productivity chart
  • Ensure 3D / TSV content consistent with other
    chapters
  • Improve DFM section, including Design for
    reliability rows
  • Overhaul of Verification , L/C/P sections
  • System Drivers chapter
  • Update MPU frequency roadmap (flat trend),
    evaluate impact
  • Update of SOC-CP and SOC-CS models (driven from
    TWGs)
  • Update AMS/RF Driver / fabric with Wireless TWG
  • More-Than-Moore RFAMS driver SiP-SoC (based on
    SoC-P)
  • Other Cross-TWG and public activity
  • PIDS increase design-driven requirements
    definition
  • 3D/TSV hold for ACTION
  • Continue other key interactions AP,
    Interconnect, Test
  • Incorporate input from 2nd EDA Roadmap Workshop
    (_at_DAC)

19
ITRS-iNEMI MTM SOC/SIP Design/IntegrationUpdate
of ITRS and iNEMI Portable Drivers
h
  • Inclusion of AMS/RF sub-driver from ITRS AMS
    driver

PA Case Study
Power (SiP)
Power (SoC)
Equivalent cost (SoC)
Other AMS
Equivalent cost (SiP)
PA (RF)
20
Gaps in EDA (IEEE DAC Roadmap Workshop 2010
Technology
EDA nature
Metrics
20
21
Selected Messages 2010
  • Design productivity continues to be center focus
    of design technology roadmap, as scaling depends
    on time to market
  • Accurate design productivity and cost models are
    key
  • Power consumption has become the key technical
    parameter that controls feasible semiconductor
    scaling
  • Power-driven device roadmap, frequency pushed to
    flat trend
  • More Than Moore has become a necessary component
    of semiconductor product scaling
  • Mixed SiP-SoC analog-digital drivers need to be
    roadmapped
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