EECS 150 - Components and Design Techniques for Digital Systems Lec 25

1
EECS 150 - Components and Design Techniques for
Digital Systems Lec 25 Division ECC

• David Culler
• Electrical Engineering and Computer Sciences
• University of California, Berkeley
• http//www.eecs.berkeley.edu/culler
• http//www-inst.eecs.berkeley.edu/cs150

2
Division

• 1001 Quotient
• Divisor 1000 1001010 Dividend 1000
  10 101 1010 1000
  10 Remainder (or Modulo result)
• At each step, determine one bit of the quotient
• If current remainder larger than division,
  subtract and set Q bit to 1
• Otherwise, bring down a bit of the dividend and
  set Q bit to 0
• Dividend Quotient x Divisor Remainder
• sizeof(dividend) sizeof(quotient)
  sizeof(divisor)
• 3 versions of divide, successive refinement

3
32-bit DIVIDE HARDWARE Version 1

• 64-bit Divisor register, 64-bit adder/subtractor,
  64-bit Remainder register, 32-bit Quotient
  register

Shift Right
Divisor
64 bits
Shift Left
Quotient
add/sub
32 bits
Write
Remainder
Control
64 bits
4
Divide Alg. Version 1
Start Place Dividend in Remainder

• n1 steps for n-bit Quotient Rem.
• Remainder Quotient Divisor00000111 0000
  00100000
• 710 210

Remainder lt 0
Remainder? 0
Test Remainder
No lt n1 repetitions
n1 repetition?
Yes n1 repetitions (n 4 here)
5
Example initial condition
Shift Right
0010 0000
Divisor
Shift Left
0000
add/sub
Quotient
Write
0000 0111
Control
Remainder/Dividend
6
Example iter 1, step 1
Shift Right
0010 0000
Divisor
Shift Left
0000
add/sub
Quotient
Write
0000 0111
1110 0111
Control
Remainder/Dividend

• 1 rem lt rem div 7 32 --gt -25
• Check rem lt0?

7
Example iter 1, step 2b
Shift Right
0010 0000
Divisor
Shift Left
0000
add/sub
Quotient
Write
0000 0111
Control
Remainder/Dividend

• rem lt rem div
• Shift Q left, bringing in 0

8
Example iter 1, step 3
Shift Right
00010000
Divisor
Shift Left
0000
add/sub
Quotient
Write
0000 0111
Control
Remainder/Dividend

• Shift div right

9
Example Iter 2, Steps 1,2b,3
Shift Right
00010000
00001000
Divisor
Shift Left
0000
0000
add/sub
Quotient
Write
0000 0111
Control
Remainder/Dividend

• 1 rem lt rem div 7 16 --gt -9
• 2. check rem lt0? rem lt rem div sll Q, Q00
• 3. srl div

10
Example Iter 3, Steps 1,2b,3
Shift Right
00000100
Divisor
Shift Left
0000
add/sub
Quotient
Write
0000 0111
Control
Remainder/Dividend

• 1 rem lt rem div 7 8 --gt -1
• 2. check rem lt0? rem lt rem div sll Q, Q00
• 3. srl div

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Example Iter 4, Steps 1,2a,3
Shift Right
00000100
00000010
Divisor
Shift Left
0001
0000
add/sub
Quotient
Write
0000 0111
0000 0011
Control
Remainder/Dividend

• 1 rem lt rem div 7 4 --gt 3
• 2. check rem lt0? sll Q, Q01
• 3. shr div

12
Example Iter 5, Steps 1,2a,3
Shift Right
00000010
00000001
Divisor
Shift Left
0001
0011
add/sub
Quotient
Write
0000 0011
0000 0001
Control
Remainder/Dividend

• 1 rem lt rem div 3 2 --gt 1
• 2. check rem lt0? sll Q, Q01
• 3. shr div

13
Version 1 Division 7/2

• Iteration step quotient divisor remainder
• 0 Initial values 0000 0010 0000 0000 0111
• 1 1 remrem-div 0000 0010 0000 1110 0111
• 2b remlt0 ? div, sll Q, Q00 0000 0010
  0000 0000 0111
• 3 shift div right 0000 0001 0000 0000 0111
• 2 1 remrem-div 0000 0001 0000 1111 0111
• 2b remlt0 ? div, sll Q, Q00 0000 0001
  0000 0000 0111
• 3 shift div right 0000 0000 1000 0000 0111
• 3 1 remrem-div 0000 0000 1000 1111 1111
• 2b remlt0 ? div, sll Q, Q00 0000 0000
  1000 0000 0111
• 3 shift div right 0000 0000 0100 0000 0111
• 4 1 remrem-div 0000 0000 0100 0000 0011
• 2a rem?0 ? sll Q, Q01 0001 0000 0100 0000
  0011
• 3 shift div right 0001 0000 0010 0000 0011
• 5 1 remrem-div 0001 0000 0010 0000 0001
• 2a rem?0 ? sll Q, Q01 0011 0000 0010 0000
  0001
• 3 shift div right 0011 0000 0001 0000 0001

14
Observations on Divide Version 1

• 1/2 bits in divisor always 0? 1/2 of 2n-bit
  adder is wasted? 1/2 of 2n-bit divisor is wasted
• Instead of shifting divisor to right, shift
  remainder to left?
• 1st step cannot produce a 1 in quotient bit
  (otherwise quotient ? 2n) ? switch order to
  shift first and then subtract, can save 1
  iteration

15
DIVIDE HARDWARE Version 2

• 32-bit Divisor register, 32-bit ALU, 64-bit
  Remainder register, 32-bit Quotient register

Divisor
32 bits
Shift Left
Quotient
32 bits
add/sub
Shift Left
Remainder
Control
Write
64 bits
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Divide Alg. Version 2
Start Place Dividend in Remainder

• Remainder Quotient Divisor
• 00000111 0000 0010
• 710 210

Remainder ? 0
Remainder lt 0
Test Remainder
nth repetition?
No lt n repetitions
Yes n repetitions (n 4 here)
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Example V2 7/2 initial conditions
Divisor
0010
Shift Left
0000
Quotient
add/sub
Shift Left
00000111
Control
Write
Remainder
18
Example V2 7/2 iter 1
Divisor
0010
Shift Left
0000
0000
Quotient
add/sub
Shift Left
11101110
00001110
00000111
00001110
Control
Write
Remainder

• 1. Shift left rem
• 2. sub remLH lt- remLH div 0 2
• Test remLH lt 0
• 3b restore remLH lt- remLH div
• Shift 0 into Q

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Announcements

• Dec 9, last day of class will do HKN survey
• Final mid term Dec 15 1230 330 in 1 LECONTE
• EECS in the news
• Recovery Oriented Computing
• Joint with Stanford!
• Availability MTBF / (MTBF Time to Repair)
• Historically focus on increasing MTBF
• ROC focuses on reducing Time to Restart
• Isolation and Redundancy
• System-wide support for Undo
• Integrated Diagnostic Support.
• Online Verification of Recovery Mechanisms.
• Design for high modularity, measurability, and
  restartability. 
• Dependability/Availability Benchmarking.

Dave Patterson
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Observations on Divide Version 2

• Eliminate Quotient register by combining with
  Remainder as shifted left.
• Start by shifting the Remainder left as before.
• Thereafter loop contains only two steps because
  the shifting of the Remainder register shifts
  both the remainder in the left half and the
  quotient in the right half
• The consequence of combining the two registers
  together and the new order of the operations in
  the loop is that the remainder will shifted left
  one time too many.
• Thus the final correction step must shift back
  only the remainder in the left half of the
  register

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DIVIDE HARDWARE Version 3

• 32-bit Divisor register, 32-bit adder/subtractor,
  64-bit Remainder register, (0-bit Quotient reg)

Divisor
32 bits
32-bit ALU
HI
LO
Shift Left
Remainder
(Quotient)
Control
Write
64 bits
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Divide Algorithm Version 3

• Remainder Divisor0000 0111 0010
• 710 210

Remainder lt 0
Remainder ? 0
Test Remainder
upper-half
No lt n repetitions
nth repetition?
Yes n repetitions (n 4 here)
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Observations on Divide Version 3

• Same Hardware as shift and add multiplier just
  63-bit register to shift left or shift right
• Signed divides Simplest is to remember signs,
  make positive, and complement quotient and
  remainder if necessary
• Note Dividend and Remainder must have same sign
• Note Quotient negated if Divisor sign Dividend
  sign disagreee.g., 7 2 3, remainder 1

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Error Correction Codes (ECC)

• Memory systems generate errors (accidentally
  flipped-bits)
• DRAMs store very little charge per bit
• Soft errors occur occasionally when cells are
  struck by alpha particles or other environmental
  upsets.
• Less frequently, hard errors can occur when
  chips permanently fail.
• Problem gets worse as memories get denser and
  larger
• Where is perfect memory required?
• servers, spacecraft/military computers, ebay,
• Memories are protected against failures with ECCs
• Extra bits are added to each data-word
• used to detect and/or correct faults in the
  memory system
• in general, each possible data word value is
  mapped to a unique code word. A fault changes
  a valid code word to an invalid one - which can
  be detected.

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Correcting Code Concept
Space of possible bit patterns (2N)

• Detection bit pattern fails codeword check
• Correction map to nearest valid code word

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Simple Error Detection Coding
Parity Bit

• Each data value, before it is written to memory
  is tagged with an extra bit to force the stored
  word to have even parity

• Each word, as it is read from memory is checked
  by finding its parity (including the parity bit).
  

• A non-zero parity indicates an error occurred
• two errors (on different bits) is not detected
  (nor any even number of errors)
• odd numbers of errors are detected.
• What is the probability of multiple simultaneous
  errors?

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Hamming Error Correcting Code

• Use more parity bits to pinpoint bit(s) in error,
  so they can be corrected.
• Example Single error correction (SEC) on 4-bit
  data
• use 3 parity bits, with 4-data bits results in
  7-bit code word
• 3 parity bits sufficient to identify any one of 7
  code word bits
• overlap the assignment of parity bits so that a
  single error in the 7-bit work can be corrected
• Procedure group parity bits so they correspond
  to subsets of the 7 bits
• p1 protects bits 1,3,5,7
• p2 protects bits 2,3,6,7
• p3 protects bits 4,5,6,7

• 1 2 3 4 5 6 7
• p1 p2 d1 p3 d2 d3 d4
• Bit position number
• 001 110
• 011 310
• 101 510
• 111 710
• 010 210
• 011 310
• 110 610
• 111 710
• 100 410
• 101 510
• 110 610
• 111 710

Note number bits from left to right.
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Hamming Code Example

• Example c c3c2c1 101
• error in 4,5,6, or 7 (by c31)
• error in 1,3,5, or 7 (by c11)
• no error in 2, 3, 6, or 7 (by c20)
• Therefore error must be in bit 5.
• Note the check bits point to 5
• By our clever positioning and assignment of
  parity bits, the check bits always address the
  position of the error!
• c000 indicates no error
• eight possibilities

• 1 2 3 4 5 6 7
• p1 p2 d1 p3 d2 d3 d4
• Note parity bits occupy power-of-two bit
  positions in code-word.
• On writing to memory
• parity bits are assigned to force even parity
  over their respective groups.
• On reading from memory
• check bits (c3,c2,c1) are generated by finding
  the parity of the group and its parity bit. If
  an error occurred in a group, the corresponding
  check bit will be 1, if no error the check bit
  will be 0.
• check bits (c3,c2,c1) form the position of the
  bit in error.

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Interactive Quiz
1 2 3 4 5 6 7 positions 001 010 011 100 101 110
111 P1 P2 d1 P3 d2 d3 d4 role
Position of error C3C2C1 Where Ci is parity of
group i

• You receive
• 1111110
• 0000010
• 1010010
• What is the correct value?

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Hamming Error Correcting Code

• Overhead involved in single error correction
  code
• let p be the total number of parity bits and d
  the number of data bits in a p d bit word.
• If p error correction bits are to point to the
  error bit (p d cases) plus indicate that no
  error exists (1 case), we need
• 2p gt p d 1,
• thus p gt log(p d 1)
• for large d, p approaches log(d)
• 8 data gt 4 parity
• 16 data gt 5 parity
• 32 data gt 6 parity
• 64 data gt 7 parity

• Adding on extra parity bit covering the entire
  word can provide double error detection
• 1 2 3 4 5 6 7 8
• p1 p2 d1 p3 d2 d3 d4 p4
• On reading the C bits are computed (as usual)
  plus the parity over the entire word, P
• C0 P0, no error
• C!0 P1, correctable single error
• C!0 P0, a double error occurred
• C0 P1, an error occurred in p4 bit

Typical modern codes in DRAM memory
systems 64-bit data blocks (8 bytes) with
72-bit code words (9 bytes).
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Summary

• Arithmetic
• Addition, subtraction, multiplication, division
  follow the rules you learned as a child, but in
  base 2
• Iterative Multiplication and Division are
  essentially same circuit
• Clever book keeping so n-bit add/sub using n-bit
  register and 2n-bit shift register
• tricks to avoid sub/check/add restore???
• See Booths Alg tricks below for multiply (if
  time)
• Error coding
• Map data word into larger code word
• Hamming distance is number of bit flips between
  symbols
• Parity detects errors of hamming distance 1
• Overlapping parity detects 2 and corrects 1
  (SECDED)

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Motivation for Booths Algorithm

• Example 2 x 6 0010 x 0110
  0010 x 0110 0000 shift (0 in
  multiplier) 0010 add (1 in
  multiplier) 0010 add (1 in
  multiplier) 0000 shift (0 in
  multiplier) 00001100
• If ALU can subtract as well as add, get same
  result as follows 6 2 8 0110
  00010 01000 11110 01000
• For example
• 0010 x 0110 0000 shift (0
  in multiplier) 0010 sub(first 1 in
  multiplier) 0000 shift (mid string
  of 1s) 0010 add (prior step had
  last 1) 00001100

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Booth Multiplier an Introduction

• Recode each 1 in multiplier as 2-1
• Converts sequences of 1 to 100(-1)
• Might reduce the number of 1s

0 0 1 1 1 1 1 1 0 0 1 -1 1
-1 1 -1 1 -1 1 -1 1 -1 0 1 0 0
0 0 0 -1 0 0
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Recoding (Encoding) Example
0 1 1 0 1 1 1 0
0 0 1 0 (1 -1)
(1 -1) (1 -1) (1
-1) (1 -1) (1
-1) 1 0 -1 1 0 0 -1 0
0 1 -1 0

• If you use the last row in multiplication, you
  should get exactly the same result as using the
  first row (after all, they represent the same
  number!)

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Booth Multiplication Example
0 0 1 1 0 6x 0 1 1 1
0 14 1 0 0 -1 0 0 0 0 0
0 1 1 0 1 0 (-6) 0 0 0 0
0 0 0 0 0 0 0 0 1 1 0 0 0 1 0
1 0 1 0 0 84
1 1 1
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Booths Alg Implementation Approach
beginning of run
end of run
middle of run
0 1 1 1 1 0

• Current Bit Bit to the Right Explanation Example O
  p
• 1 0 Begins run of 1s 0001111000 sub
• 1 1 Middle of run of 1s 0001111000 none
• 0 1 End of run of 1s 0001111000 add
• 0 0 Middle of run of 0s 0001111000 none
• Originally for Speed (when shift is faster than
  add, it is advantageous to replace adds and subs
  with shifts)
• Basic idea replace a string of 1s in multiplier
  with an initial subtract for rightmost 1 in a run
  of 1s, then later add back a 1 for the bit to
  the left of the last 1 in the run

1 10000 01111
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Booths Example (2 x 7)
Operation Multiplicand Product next? 0. initial
value 0010 0000 0111 0 10 -gt sub

• 1a. P P - m 1110
  1110 1110 0111 0 shift P
  (sign ext)
• 1b. 0010 1111 0011 1 11 -gt
  nop, shift
• 2. 0010 1111 1001 1 11 -gt
  nop, shift
• 3. 0010 1111 1100 1 01 -gt add
• 4a. 0010 0010
  0001 1100 1 shift
• 4b. 0010 0000 1110 0 done

38
Booths Example (2 x -3)
Operation Multiplicand Product next? 0. initial
value 0010 0000 1101 0 10 -gt sub

• 1a. P P - m 1110
  1110 1110 1101 0 shift P
  (sign ext)
• 1b. 0010 1111 0110 1 01 -gt add
  0010
• 2a. 0001 0110 1 shift P
• 2b. 0010 0000 1011 0 10 -gt sub
  1110
• 3a. 0010 1110 1011 0 shift
• 3b. 0010 1111 0101 1 11 -gt nop
• 4a 1111 0101 1 shift
• 4b. 0010 1111 1010 1 done