Chip Carrier Package as an Alternative for Known Good Die

1
Chip Carrier Package as an Alternative for Known
Good Die

• Raymond Kuang

September 08, 2004
2
Driver for Known Good Die (KGD)

• Applications which require integration of
  different die technologies in one board
  (Multi-Chip- Package, System-in-Package, etc) and
  where the cost of board rework due to bad die is
  severe.
• Major markets are portable electronic products.
• The advent of small footprint packages like Chip
  Scale, Wafer Scale, etc offers a low cost
  alternative for low end applications.
• High end systems which require limited weight
  and space.

3
Limitation of KGD

• High end KGD for high end application is
  difficult to obtain.
• Limited to small I/O devices due to technical
  difficulties.
• Full screening through the fine bond pad pitch
  in todays sub-micron silicon technology is an
  issue.
• Each die size for KGD normally requires custom
  socket.
• Marking for traceability, such as wafer lot, is
  not possible.
• Mil-Std-883 requires traceability for Space
  Application devices.

4
Chip Carrier as an Alternative Solution for KGD
17 mm
17 mm
Total Thickness 1.847 mm
256 Bond fingers on edges of package
5
Chip Carrier as an Alternative Solution for KGD

• Advantages
• Designed for high density I/O where bare die
  testing is not technically and economically
  feasible.
• Testing and Programming the device through the
  package terminal is reliable.
• Voltage and currents are controlled with the use
  of low socket
• impedance.
• Testing and programming are same as package parts
  like BGA or LGA. They are cost effective and
  reliable
• Can accommodate many die sizes in one Chip
  Carrier package outline.
• No custom socket is needed for each die
  configuration.
• Can be marked for unit traceability (wafer lot,
  etc).

6
Chip Carrier as an Alternative Solution for KGD
cont

• Features
• Small Foot print.
• Can be used for both wire bond and flip chip
  version.
• Wire bond version.
• Smallest size is around bare die size 6.5 mm.
• Flip Chip version.
• Smallest size is bare die size 5.0 mm.

Lead finger for wire bond use
Pads for Test/Programming use or BGA connection
7
Chip Carrier as an Alternative Solution for KGD
cont

• Two terminals available for each signal
• External lead fingers on the top sides for
  wire bond from package to MCM use.
• Land grid pads at the bottom primarily for test
  use. Can be utilized for BGA connection to the
  MCM board also.
• Chip Carrier material can be ceramic, organic or
  other suitable materials.
• Multi-layer build-up substrate to enhance
  electrical performance and routing for high
  density I/O applications.

8
Method to Integrate into MCM

• Wire bond top lead fingers to system board to
  route out signal.
• Chip Carrier must be attached using electrically
  non-conductive epoxy to system board.

Wire bond version
Flip Chip version
9
Method to Integrate into MCMcont

• Use the land pads at the bottom of the package.
• Chip Carrier can be connected using solder balls
  and reflow to the system board.

Wire bond version
Flip Chip version
10
Manufacturing Issue and solution

• Major concern is contamination on external bond
  fingers that may affect board level wire bonding
  reliability.
• Due to poor handling at assembly and test, and
  equipment cleanliness.
• use of contaminated finger cots in handling the
  unit, use of contaminated perfluorocarbon bath
  at gross leak test, out gassing from contaminated
  burn-in board, etc
• Handling-induced contamination can be prevented
  by the use of clean vacuum pen to pick and
  place the units.

11
Manufacturing Issue and solution cont

• A good control to prevent contamination of
  accessories like trays/boats, sockets, etc. use
  in the assembly and test of the parts must be in
  place.
• Use of low power microscope at visual inspection
  is necessary.
• Wet cleaning using Isopropyl Alcohol can be used
  to remove most surface contamination induced
  during assembly and test screening.
• Recommended to do plasma cleaning prior to wire
  bonding at Multi-Chip-Module or board level
  assembly.

12
Bond Finger Reliability at Board Level

• Chip Carrier units were exposed to different
  handling conditions, attached and wire bonded to
  a ceramic package and aged at 150C environment. A
  bond pull test was done to determine the
  interconnect reliability.

Gold bond
13
Reliability Evaluation cont

• Details

14
Reliability Evaluation cont

• Notes
• Cleaning process
• Wet used Isopropyl Alcohol, and de-ionized (DI)
  water.
• Plasma used 100 Argon gas
• Bond pull Strength test Sample size
• As-bonded 50-65 wires/unit
• Post 500 hrs HTS 100 wires/unit
• Wire bond Strength Pull modes
• 1 break at neck above the ball
• 2 break at wire span
• 4 break at wedge bond

15
Reliability Evaluation cont

• The bond strength pull mode were at wire neck
  above the gold ball, and at wire span.
• The absence of gold ball-to-lead finger
  separation indicates good gold wire bonding to
  Chip Carriers lead finger.
• The bond strength measured on samples were above
  the Mil-Std-883 TM2011 minimum requirement.

16
Summary

• Actels near-die size Chip Carrier is a viable
  alternative for Known-good-die (KGD). It
  eliminate the challenges associated with
  handling, testing, and programming of todays
  high I/O, high density devices in bare die
  format.
• Chip Carrier can be used in both flip chip or
  wire bonding format.
• A slight deposit of contamination coming from the
  environment and handling during assembly and test
  is expected on external bond fingers of Chip
  Carrier. However, this can be controlled by
  implementing good handling and cleaning procedure.

Thanks!