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Supercomputing in Plain English Part VIII: Multicore Madness

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Title: Supercomputing in Plain English Part VIII: Multicore Madness


1
Supercomputingin Plain EnglishPart VIII
Multicore Madness
  • Henry Neeman, Director
  • OU Supercomputing Center for Education Research
  • University of Oklahoma Information Technology
  • Tuesday April 14 2009

2
This is an experiment!
  • Its the nature of these kinds of
    videoconferences that FAILURES ARE GUARANTEED TO
    HAPPEN! NO PROMISES!
  • So, please bear with us. Hopefully everything
    will work out well enough.
  • If you lose your connection, you can retry the
    same kind of connection, or try connecting
    another way.
  • Remember, if all else fails, you always have the
    toll free phone bridge to fall back on.

3
Access Grid
  • This weeks Access Grid (AG) venue Cactus.
  • If you arent sure whether you have AG, you
    probably dont.

Tue Apr 14 Cactus
Tue Apr 21 Verlet
Tue Apr 28 Cactus
Tue May 5 Titan
Many thanks to John Chapman of U Arkansas for
setting these up for us.
4
H.323 (Polycom etc)
  • If you want to use H.323 videoconferencing for
    example, Polycom then dial
  • 69.77.7.20312345
  • any time after 200pm. Please connect early, at
    least today.
  • For assistance, contact Andy Fleming of
    KanREN/Kan-ed (afleming_at_kanren.net or
    785-230-2513).
  • KanREN/Kan-eds H.323 system can handle up to 40
    simultaneous H.323 connections. If you cannot
    connect, it may be that all 40 are already in
    use.
  • Many thanks to Andy and KanREN/Kan-ed for
    providing H.323 access.

5
iLinc
  • We have unlimited simultaneous iLinc connections
    available.
  • If youre already on the SiPE e-mail list, then
    you should receive an e-mail about iLinc before
    each session begins.
  • If you want to use iLinc, please follow the
    directions in the iLinc e-mail.
  • For iLinc, you MUST use either Windows (XP
    strongly preferred) or MacOS X with Internet
    Explorer.
  • To use iLinc, youll need to download a client
    program to your PC. Its free, and setup should
    take only a few minutes.
  • Many thanks to Katherine Kantardjieff of
    California State U Fullerton for providing the
    iLinc licenses.

6
QuickTime Broadcaster
  • If you cannot connect via the Access Grid, H.323
    or iLinc, then you can connect via QuickTime
  • rtsp//129.15.254.141/test_hpc09.sdp
  • We recommend using QuickTime Player for this,
    because weve tested it successfully.
  • We recommend upgrading to the latest version at
  • http//www.apple.com/quicktime/
  • When you run QuickTime Player, traverse the menus
  • File -gt Open URL
  • Then paste in the rstp URL into the textbox, and
    click OK.
  • Many thanks to Kevin Blake of OU for setting up
    QuickTime Broadcaster for us.

7
Phone Bridge
  • If all else fails, you can call into our toll
    free phone bridge
  • 1-866-285-7778, access code 6483137
  • Please mute yourself and use the phone to listen.
  • Dont worry, well call out slide numbers as we
    go.
  • Please use the phone bridge ONLY if you cannot
    connect any other way the phone bridge is
    charged per connection per minute, so our
    preference is to minimize the number of
    connections.
  • Many thanks to Amy Apon and U Arkansas for
    providing the toll free phone bridge.

8
Please Mute Yourself
  • No matter how you connect, please mute yourself,
    so that we cannot hear you.
  • At OU, we will turn off the sound on all
    conferencing technologies.
  • That way, we wont have problems with echo
    cancellation.
  • Of course, that means we cannot hear questions.
  • So for questions, youll need to send some kind
    of text.
  • Also, if youre on iLinc SIT ON YOUR HANDS!
  • Please DONT touch ANYTHING!

9
Questions via Text iLinc or E-mail
  • Ask questions via text, using one of the
    following
  • iLincs text messaging facility
  • e-mail to sipe2009_at_gmail.com.
  • All questions will be read out loud and then
    answered out loud.

10
Thanks for helping!
  • OSCER operations staff (Brandon George, Dave
    Akin, Brett Zimmerman, Josh Alexander)
  • OU Research Campus staff (Patrick Calhoun, Josh
    Maxey, Gabe Wingfield)
  • Kevin Blake, OU IT (videographer)
  • Katherine Kantardjieff, CSU Fullerton
  • John Chapman and Amy Apon, U Arkansas
  • Andy Fleming, KanREN/Kan-ed
  • This material is based upon work supported by the
    National Science Foundation under Grant No.
    OCI-0636427, CI-TEAM Demonstration
    Cyberinfrastructure Education for Bioinformatics
    and Beyond.

11
This is an experiment!
  • Its the nature of these kinds of
    videoconferences that FAILURES ARE GUARANTEED TO
    HAPPEN! NO PROMISES!
  • So, please bear with us. Hopefully everything
    will work out well enough.
  • If you lose your connection, you can retry the
    same kind of connection, or try connecting
    another way.
  • Remember, if all else fails, you always have the
    toll free phone bridge to fall back on.

12
Supercomputing Exercises
  • Want to do the Supercomputing in Plain English
    exercises?
  • The first several exercises are already posted
    at
  • http//www.oscer.ou.edu/education.php
  • If you dont yet have a supercomputer account,
    you can get a temporary account, just for the
    Supercomputing in Plain English exercises, by
    sending e-mail to
  • hneeman_at_ou.edu
  • Please note that this account is for doing the
    exercises only, and will be shut down at the end
    of the series.

13
OK Supercomputing Symposium 2009
2004 Keynote Sangtae Kim NSF Shared Cyberinfrastr
ucture Division Director
2003 Keynote Peter Freeman NSF Computer
Information Science Engineering Assistant
Director
  • 2006 Keynote
  • Dan Atkins
  • Head of NSFs
  • Office of
  • Cyber-
  • infrastructure

2005 Keynote Walt Brooks NASA Advanced Supercompu
ting Division Director
2007 Keynote Jay Boisseau Director Texas
Advanced Computing Center U. Texas Austin
2008 Keynote José Munoz Deputy Office Director/
Senior Scientific Advisor Office of Cyber-
infrastructure National Science Foundation
2009 Keynote Ed Seidel Director NSF Office
of Cyber-infrastructure
FREE! Wed Oct 7 2009 _at_ OU Over 235 registrations
already! Over 150 in the first day, over 200 in
the first week, over 225 in the first month.
http//symposium2009.oscer.ou.edu/
Parallel Programming Workshop FREE!
Tue Oct 6 2009 _at_ OU
Sponsored by SC09 Education Program FREE!
Symposium Wed Oct 7 2009 _at_ OU
14
SC09 Summer Workshops
  • This coming summer, the SC09 Education Program,
    part of the SC09 (Supercomputing 2009)
    conference, is planning to hold two weeklong
    supercomputing-related workshops in Oklahoma, for
    FREE (except you pay your own transport)
  • At OSU Sun May 17 the May 23
  • FREE Computational Chemistry for Chemistry
    Educators
  • (2010 TENTATIVE Computational Biology)
  • At OU Sun Aug 9 Sat Aug 15
  • FREE Parallel Programming Cluster Computing
  • Well alert everyone when the details have been
    ironed out and the registration webpage opens.
  • Please note that you must apply for a seat, and
    acceptance CANNOT be guaranteed.

15
SC09 Summer Workshops
  1. May 17-23 Oklahoma State U Computational
    Chemistry
  2. May 25-30 Calvin Coll (MI) Intro to
    Computational Thinking
  3. June 7-13 U Cal Merced Computational Biology
  4. June 7-13 Kean U (NJ) Parallel Progrmg
    Cluster Comp
  5. June 14-20 Widener U (PA) Computational Physics
  6. July 5-11 Atlanta U Ctr Intro to Computational
    Thinking
  7. July 5-11 Louisiana State U Parallel Progrmg
    Cluster Comp
  8. July 12-18 U Florida Computational Thinking
    Grades 6-12
  9. July 12-18 Ohio Supercomp Ctr Computational
    Engineering
  10. Aug 2- 8 U Arkansas Intro to Computational
    Thinking
  11. Aug 9-15 U Oklahoma Parallel Progrmg
    Cluster Comp

16
Outline
  • The March of Progress
  • Multicore/Many-core Basics
  • Software Strategies for Multicore/Many-core
  • A Concrete Example Weather Forecasting

17
The March of Progress
18
OUs TeraFLOP Cluster, 2002
  • 10 racks _at_ 1000 lbs per rack
  • 270 Pentium4 Xeon CPUs, 2.0 GHz,
    512 KB L2 cache
  • 270 GB RAM, 400 MHz FSB
  • 8 TB disk
  • Myrinet2000 Interconnect
  • 100 Mbps Ethernet Interconnect
  • OS Red Hat Linux
  • Peak speed 1.08 TFLOPs
  • (1.08 trillion calculations per second)
  • One of the first Pentium4 clusters!

boomer.oscer.ou.edu
19
TeraFLOP, Prototype 2006, Sale 2011
9 years from room to chip!
http//news.com.com/2300-1006_3-6119652.html
20
Moores Law
  • In 1965, Gordon Moore was an engineer at
    Fairchild Semiconductor.
  • He noticed that the number of transistors that
    could be squeezed onto a chip was doubling about
    every 18 months.
  • It turns out that computer speed is roughly
    proportional to the number of transistors per
    unit area.
  • Moore wrote a paper about this concept, which
    became known as Moores Law.

21
Moores Law in Practice
CPU
log(Speed)
Year
22
Moores Law in Practice
Network Bandwidth
CPU
log(Speed)
Year
23
Moores Law in Practice
Network Bandwidth
CPU
log(Speed)
RAM
Year
24
Moores Law in Practice
Network Bandwidth
CPU
log(Speed)
RAM
1/Network Latency
Year
25
Moores Law in Practice
Network Bandwidth
CPU
log(Speed)
RAM
1/Network Latency
Software
Year
26
Fastest Supercomputer vs. Moore
GFLOPs billions of calculations per second
27
The Tyranny ofthe Storage Hierarchy
28
The Storage Hierarchy
Fast, expensive, few
  • Registers
  • Cache memory
  • Main memory (RAM)
  • Hard disk
  • Removable media (CD, DVD etc)
  • Internet

Slow, cheap, a lot
29
RAM is Slow
CPU
351 GB/sec6
The speed of data transfer between Main Memory
and the CPU is much slower than the speed of
calculating, so the CPU spends most of its time
waiting for data to come in or go out.
Bottleneck
3.4 GB/sec7 (1)
30
Why Have Cache?
CPU
Cache is much closer to the speed of the CPU, so
the CPU doesnt have to wait nearly as long
for stuff thats already in cache it can do
more operations per second!
14.2 GB/sec (4x RAM)7
3.4 GB/sec7 (1)
31
Henrys Laptop
  • Pentium 4 Core Duo T2400 1.83 GHz w/2
    MB L2 Cache (Yonah)
  • 2 GB (2048 MB) 667
    MHz DDR2 SDRAM
  • 100 GB 7200 RPM SATA Hard Drive
  • DVDRW/CD-RW Drive (8x)
  • 1 Gbps Ethernet Adapter
  • 56 Kbps Phone Modem

Dell Latitude D6204
32
Storage Speed, Size, Cost
Henrys Laptop Registers (Pentium 4 Core Duo 1.83 GHz) Cache Memory (L2) Main Memory (667 MHz DDR2 SDRAM) Hard Drive (SATA 7200 RPM) Ethernet (1000 Mbps) DVDRW (8x) Phone Modem (56 Kbps)
Speed (MB/sec) peak 359,7926 (14,640 MFLOP/s) 14,500 7 3400 7 100 9 125 10.8 10 0.007
Size (MB) 304 bytes 11 2 2048 100,000 unlimited unlimited unlimited
Cost (/MB) 5 12 0.03 12 0.0001 12 charged per month (typically) 0.00003 12 charged per month (typically)
MFLOP/s millions of floating point
operations per second 8 32-bit integer
registers, 8 80-bit floating point registers, 8
64-bit MMX integer registers, 8 128-bit
floating point XMM registers
33
Storage Use Strategies
  • Register reuse Do a lot of work on the same data
    before working on new data.
  • Cache reuse The program is much more efficient
    if all of the data and instructions fit in cache
    if not, try to use whats in cache a lot before
    using anything that isnt in cache.
  • Data locality Try to access data that are near
    each other in memory before data that are far.
  • I/O efficiency Do a bunch of I/O all at once
    rather than a little bit at a time dont mix
    calculations and I/O.

34
A Concrete Example
  • OSCERs big cluster, Sooner, has Harpertown CPUs
    quad core, 2.0 GHz, 1333 MHz Front Side
    Bus.
  • The theoretical peak CPU speed is 32 GFLOPs
    (double precision) per CPU, and in practice weve
    gotten as high as 93 of that. For a dual chip
    node, the peak is 64 GFLOPs.
  • Each double precision calculation is 2 8-byte
    operands and one 8-byte result, so 24 bytes get
    moved between RAM and CPU.
  • So, in theory each node could transfer up to 1536
    GB/sec.
  • The theoretical peak RAM bandwidth is 21 GB/sec
    (but in practice we get about 3.4 GB/sec).
  • So, even at theoretical peak, any code that does
    less than 73 calculations per byte transferred
    between RAM and cache has speed limited by RAM
    bandwidth.

35
Good Cache Reuse Example
36
A Sample Application
  • Matrix-Matrix Multiply
  • Let A, B and C be matrices of sizes
  • nr ? nc, nr ? nk and nk ? nc, respectively

The definition of A B C is
for r ? 1, nr, c ? 1, nc.
37
Matrix Multiply Naïve Version
  • SUBROUTINE matrix_matrix_mult_naive (dst, src1,
    src2,
  • nr, nc, nq)
  • IMPLICIT NONE
  • INTEGER,INTENT(IN) nr, nc, nq
  • REAL,DIMENSION(nr,nc),INTENT(OUT) dst
  • REAL,DIMENSION(nr,nq),INTENT(IN) src1
  • REAL,DIMENSION(nq,nc),INTENT(IN) src2
  • INTEGER r, c, q
  • DO c 1, nc
  • DO r 1, nr
  • dst(r,c) 0.0
  • DO q 1, nq
  • dst(r,c) dst(r,c) src1(r,q)
    src2(q,c)
  • END DO
  • END DO
  • END DO
  • END SUBROUTINE matrix_matrix_mult_naive

38
Performance of Matrix Multiply
39
Tiling
40
Tiling
  • Tile A small rectangular subdomain of a problem
    domain. Sometimes called a block or a chunk.
  • Tiling Breaking the domain into tiles.
  • Tiling strategy Operate on each tile to
    completion, then move to the next tile.
  • Tile size can be set at runtime, according to
    whats best for the machine that youre running
    on.

41
Tiling Code
  • SUBROUTINE matrix_matrix_mult_by_tiling (dst,
    src1, src2, nr, nc, nq,
  • rtilesize, ctilesize, qtilesize)
  • IMPLICIT NONE
  • INTEGER,INTENT(IN) nr, nc, nq
  • REAL,DIMENSION(nr,nc),INTENT(OUT) dst
  • REAL,DIMENSION(nr,nq),INTENT(IN) src1
  • REAL,DIMENSION(nq,nc),INTENT(IN) src2
  • INTEGER,INTENT(IN) rtilesize, ctilesize,
    qtilesize
  • INTEGER rstart, rend, cstart, cend, qstart,
    qend
  • DO cstart 1, nc, ctilesize
  • cend cstart ctilesize - 1
  • IF (cend gt nc) cend nc
  • DO rstart 1, nr, rtilesize
  • rend rstart rtilesize - 1
  • IF (rend gt nr) rend nr
  • DO qstart 1, nq, qtilesize
  • qend qstart qtilesize - 1

42
Multiplying Within a Tile
  • SUBROUTINE matrix_matrix_mult_tile (dst, src1,
    src2, nr, nc, nq,
  • rstart, rend, cstart, cend,
    qstart, qend)
  • IMPLICIT NONE
  • INTEGER,INTENT(IN) nr, nc, nq
  • REAL,DIMENSION(nr,nc),INTENT(OUT) dst
  • REAL,DIMENSION(nr,nq),INTENT(IN) src1
  • REAL,DIMENSION(nq,nc),INTENT(IN) src2
  • INTEGER,INTENT(IN) rstart, rend, cstart,
    cend, qstart, qend
  • INTEGER r, c, q
  • DO c cstart, cend
  • DO r rstart, rend
  • IF (qstart 1) dst(r,c) 0.0
  • DO q qstart, qend
  • dst(r,c) dst(r,c) src1(r,q)
    src2(q,c)
  • END DO
  • END DO
  • END DO

43
Reminder Naïve Version, Again
  • SUBROUTINE matrix_matrix_mult_naive (dst, src1,
    src2,
  • nr, nc, nq)
  • IMPLICIT NONE
  • INTEGER,INTENT(IN) nr, nc, nq
  • REAL,DIMENSION(nr,nc),INTENT(OUT) dst
  • REAL,DIMENSION(nr,nq),INTENT(IN) src1
  • REAL,DIMENSION(nq,nc),INTENT(IN) src2
  • INTEGER r, c, q
  • DO c 1, nc
  • DO r 1, nr
  • dst(r,c) 0.0
  • DO q 1, nq
  • dst(r,c) dst(r,c) src1(r,q)
    src2(q,c)
  • END DO
  • END DO
  • END DO
  • END SUBROUTINE matrix_matrix_mult_naive

44
Performance with Tiling
45
The Advantages of Tiling
  • It allows your code to exploit data locality
    better, to get much more cache reuse your code
    runs faster!
  • Its a relatively modest amount of extra coding
    (typically a few wrapper functions and some
    changes to loop bounds).
  • If you dont need tiling because of the
    hardware, the compiler or the problem size then
    you can turn it off by simply setting the tile
    size equal to the problem size.

46
Why Does Tiling Work Here?
  • Cache optimization works best when the number of
    calculations per byte is large.
  • For example, with matrix-matrix multiply on an n
    n matrix, there are O(n3) calculations (on the
    order of n3), but only O(n2) bytes of data.
  • So, for large n, there are a huge number of
    calculations per byte transferred between RAM and
    cache.

47
Will Tiling Always Work?
  • Tiling WONT always work. Why?
  • Well, tiling works well when
  • the order in which calculations occur doesnt
    matter much, AND
  • there are lots and lots of calculations to do for
    each memory movement.
  • If either condition is absent, then tiling wont
    help.

48
Multicore/Many-core Basics
49
What is Multicore?
  • In the olden days (that is, the first half of
    2005), each CPU chip had one brain in it.
  • Starting the second half of 2005, each CPU chip
    has 2 cores (brains) starting in late 2006, 4
    cores starting in late 2008, 6 cores expected
    in late 2009, 8 cores.
  • Jargon Each CPU chip plugs into a socket, so
    these days, to avoid confusion, people refer to
    sockets and cores, rather than CPUs or
    processors.
  • Each core is just like a full blown CPU, except
    that it shares its socket with one or more other
    cores and therefore shares its bandwidth to RAM.

50
Dual Core
Core Core
51
Quad Core
Core Core Core Core
52
Oct Core
Core Core Core Core Core Core Core
Core
53
The Challenge of Multicore RAM
  • Each socket has access to a certain amount of
    RAM, at a fixed RAM bandwidth per SOCKET or
    even per node.
  • As the number of cores per socket increases, the
    contention for RAM bandwidth increases too.
  • At 2 or even 4 cores in a socket, this problem
    isnt too bad. But at 16 or 32 or 80 cores, its
    a huge problem.
  • So, applications that are cache optimized will
    get big speedups.
  • But, applications whose performance is limited by
    RAM bandwidth are going to speed up only as fast
    as RAM bandwidth speeds up.
  • RAM bandwidth speeds up much slower than CPU
    speeds up.

54
The Challenge of Multicore Network
  • Each node has access to a certain number of
    network ports, at a fixed number of network ports
    per NODE.
  • As the number of cores per node increases, the
    contention for network ports increases too.
  • At 2 or 4 cores in a socket, this problem isnt
    too bad. But at 16 or 32 or 80 cores, its a huge
    problem.
  • So, applications that do minimal communication
    will get big speedups.
  • But, applications whose performance is limited by
    the number of MPI messages are going to speed up
    very very little and may even crash the node.

55
A Concrete ExampleWeather Forecasting
56
Weather Forecasting
http//www.caps.ou.edu/wx/p/r/conus/fcst/
57
Weather Forecasting
  • Weather forecasting is a transport problem.
  • The goal is to predict future weather conditions
    by simulating the movement of fluids in Earths
    atmosphere.
  • The physics is the Navier-Stokes Equations.
  • The numerical method is Finite Difference.

58
Cartesian Mesh
59
Finite Difference
  • unew(i,j,k) F(uold, i, j, k, ?t)
  • F(uold(i,j,k),
  • uold(i-1,j,k), uold(i1,j,k),
  • uold(i,j-1,k), uold(i,j1,k),
  • uold(i,j,k-1), uold(i,j,k1), ?t)

60
Ghost Boundary Zones
61
Software Strategiesfor Weather Forecastingon
Multicore/Many-core
62
Tiling NOT Good for Weather Codes
  • Weather codes typically have on the order of 150
    3D arrays used in each timestep (some transferred
    multiple times in the same timestep, but lets
    ignore that for simplicity).
  • These arrays typically are single precision (4
    bytes per floating point value).
  • So, a typical weather code uses about 600 bytes
    per mesh zone per timestep.
  • Weather codes typically do 5,000 to 10,000
    calculations per mesh zone per timestep.
  • So, the ratio of calculations to data is less
    than 20 to 1 much less than the 73 to 1 needed
    (on mid-2008 hardware).

63
Weather Forecasting and Cache
  • On current weather codes, data decomposition is
    per process. That is, each process gets one
    subdomain.
  • As CPUs speed up and RAM sizes grow, the size of
    each processors subdomain grows too.
  • However, given RAM bandwidth limitations, this
    means that performance can only grow with RAM
    speed which increases slower than CPU speed.
  • If the codes were optimized for cache, would they
    speed up more?
  • First How to optimize for cache?

64
How to Get Good Cache Reuse?
  • Multiple independent subdomains per processor.
  • Each subdomain fits entirely in L2 cache.
  • Each subdomains page table entries fit entirely
    in the TLB.
  • Expanded ghost zone stencil allows multiple
    timesteps before communicating with neighboring
    subdomains.
  • Parallelize along the Z-axis as well as X and Y.
  • Use higher order numerical schemes.
  • Reduce the memory footprint as much as possible.
  • Coincidentally, this also reduces communication
    cost.

65
Cache Optimization Strategy Tiling?
  • Would tiling work as a cache optimization
    strategy for weather forecasting codes?

66
Multiple Subdomains Per Core
Core 2
Core 0
Core 3
Core 1
67
Why Multiple Subdomains?
  • If each subdomain fits in cache, then the CPU can
    bring all the data of a subdomain into cache,
    chew on it for a while, then move on to the next
    subdomain lots of cache reuse!
  • Oh, wait, what about the TLB? Better make the
    subdomains smaller! (So more of them.)
  • But, doesnt tiling have the same effect?

68
Why Independent Subdomains?
  • Originally, the point of this strategy was to
    hide the cost of communication.
  • When you finish chewing up a subdomain, send its
    data to its neighbors non-blocking (MPI_Isend).
  • While the subdomains data is flying through the
    interconnect, work on other subdomains, which
    hides the communication cost.
  • When its time to work on this subdomain again,
    collect its data (MPI_Waitall).
  • If youve done enough work, then the
    communication cost is zero.

69
Expand the Array Stencil
  • If you expand the array stencil of each subdomain
    beyond the numerical stencil, then you dont have
    to communicate as often.
  • When you communicate, instead of sending a slice
    along each face, send a slab, with extra stencil
    levels.
  • In the first timestep after communicating, do
    extra calculations out to just inside the
    numerical stencil.
  • In subsequent timesteps, calculate fewer and
    fewer stencil levels, until its time to
    communicate again less total communication, and
    more calculations to hide the communication cost
    underneath!

70
An Extra Win!
  • If you do all this, theres an amazing side
    effect you get better cache reuse, because you
    stick with the same subdomain for a longer period
    of time.
  • So, instead of doing, say, 5000 calculations per
    zone per timestep, you can do 15000 or 20000.
  • So, you can better amortize the cost of
    transferring the data between RAM and cache.

71
New Algorithm
  • DO timestep 1, number_of_timesteps,
    extra_stencil_levels
  • DO subdomain 1, number_of_local_subdomains
  • CALL receive_messages_nonblocking(subdomai
    n,
  • timestep)
  • DO extra_stencil_level0,
    extra_stencil_levels - 1
  • CALL calculate_entire_timestep(subdoma
    in,
  • timestep
    extra_stencil_level)
  • END DO
  • CALL send_messages_nonblocking(subdomain,
  • timestep extra_stencil_levels)
  • END DO
  • END DO

72
Higher Order Numerical Schemes
  • Higher order numerical schemes are great, because
    they require more calculations per mesh zone per
    timestep, which you need to amortize the cost of
    transferring data between RAM and cache. Might as
    well!
  • Plus, they allow you to use a larger time
    interval per timestep (dt), so you can do fewer
    total timesteps for the same accuracy or you
    can get higher accuracy for the same number of
    timesteps.

73
Parallelize in Z
  • Most weather forecast codes parallelize in X and
    Y, but not in Z, because gravity makes the
    calculations along Z more complicated than X and
    Y.
  • But, that means that each subdomain has a high
    number of zones in Z, compared to X and Y.
  • For example, a 1 km CONUS run will probably have
    100 zones in Z (25 km at 0.25 km resolution).

74
Multicore/Many-core Problem
  • Most multicore chip families have relatively
    small cache per core (for example, 2 MB) and
    this problem seems likely to remain.
  • Small TLBs make the problem worse 512 KB per
    core rather than 3 MB.
  • So, to get good cache reuse, you need subdomains
    of no more than 512 KB.
  • If you have 150 3D variables at single precision,
    and 100 zones in Z, then your horizontal size
    will be 3 x 3 zones just enough for your
    stencil!

75
What Do We Need?
  • We need much bigger caches!
  • 16 MB cache ? 16 x 16 horizontal including
    stencil
  • 32 MB cache ? 23 x 23 horizontal including
    stencil
  • TLB must be big enough to cover the entire cache.
  • Itd be nice to have RAM speed increase as fast
    as core counts increase, but lets not kid
    ourselves.
  • Keep this in mind when we get to GPGPU!

76
OK Supercomputing Symposium 2009
2004 Keynote Sangtae Kim NSF Shared Cyberinfrastr
ucture Division Director
2003 Keynote Peter Freeman NSF Computer
Information Science Engineering Assistant
Director
  • 2006 Keynote
  • Dan Atkins
  • Head of NSFs
  • Office of
  • Cyber-
  • infrastructure

2005 Keynote Walt Brooks NASA Advanced Supercompu
ting Division Director
2007 Keynote Jay Boisseau Director Texas
Advanced Computing Center U. Texas Austin
2008 Keynote José Munoz Deputy Office Director/
Senior Scientific Advisor Office of Cyber-
infrastructure National Science Foundation
2009 Keynote Ed Seidel Director NSF Office
of Cyber-infrastructure
FREE! Wed Oct 7 2009 _at_ OU Over 235 registrations
already! Over 150 in the first day, over 200 in
the first week, over 225 in the first month.
http//symposium2009.oscer.ou.edu/
Parallel Programming Workshop FREE!
Tue Oct 6 2009 _at_ OU
Sponsored by SC09 Education Program FREE!
Symposium Wed Oct 7 2009 _at_ OU
77
SC09 Summer Workshops
  • This coming summer, the SC09 Education Program,
    part of the SC09 (Supercomputing 2009)
    conference, is planning to hold two weeklong
    supercomputing-related workshops in Oklahoma, for
    FREE (except you pay your own transport)
  • At OSU Sun May 17 the May 23
  • FREE Computational Chemistry for Chemistry
    Educators
  • (2010 TENTATIVE Computational Biology)
  • At OU Sun Aug 9 Sat Aug 15
  • FREE Parallel Programming Cluster Computing
  • Well alert everyone when the details have been
    ironed out and the registration webpage opens.
  • Please note that you must apply for a seat, and
    acceptance CANNOT be guaranteed.

78
SC09 Summer Workshops
  1. May 17-23 Oklahoma State U Computational
    Chemistry
  2. May 25-30 Calvin Coll (MI) Intro to
    Computational Thinking
  3. June 7-13 U Cal Merced Computational Biology
  4. June 7-13 Kean U (NJ) Parallel, Distributed
    Grid
  5. June 14-20 Widener U (PA) Computational Physics
  6. July 5-11 Atlanta U Ctr Intro to Computational
    Thinking
  7. July 5-11 Louisiana State U Parallel,
    Distributed Grid
  8. July 12-18 U Florida Computational Thinking
    Pre-college
  9. July 12-18 Ohio Supercomp Ctr Computational
    Engineering
  10. Aug 2- 8 U Arkansas Intro to Computational
    Thinking
  11. Aug 9-15 U Oklahoma Parallel, Distributed
    Grid

79
To Learn More Supercomputing
  • http//www.oscer.ou.edu/education.php

80
Thanks for helping!
  • OSCER operations staff (Brandon George, Dave
    Akin, Brett Zimmerman, Josh Alexander)
  • OU Research Campus staff (Patrick Calhoun, Josh
    Maxey, Gabe Wingfield)
  • Kevin Blake, OU IT (videographer)
  • Katherine Kantardjieff, CSU Fullerton
  • John Chapman and Amy Apon, U Arkansas
  • Andy Fleming, KanREN/Kan-ed
  • This material is based upon work supported by the
    National Science Foundation under Grant No.
    OCI-0636427, CI-TEAM Demonstration
    Cyberinfrastructure Education for Bioinformatics
    and Beyond.

81
Thanks for your attention!Questions?
82
References
1 Image by Greg Bryan, Columbia U. 2 Update
on the Collaborative Radar Acquisition Field Test
(CRAFT) Planning for the Next Steps.
Presented to NWS Headquarters August 30 2001. 3
See http//hneeman.oscer.ou.edu/hamr.html for
details. 4 http//www.dell.com/ 5
http//www.vw.com/newbeetle/ 6 Richard Gerber,
The Software Optimization Cookbook
High-performance Recipes for the Intel
Architecture. Intel Press, 2002, pp. 161-168. 7
RightMark Memory Analyzer. http//cpu.rightmark.or
g/ 8 ftp//download.intel.com/design/Pentium4/p
apers/24943801.pdf 9 http//www.seagate.com/cda
/products/discsales/personal/family/0,1085,621,00.
html 10 http//www.samsung.com/Products/OpticalD
iscDrive/SlimDrive/OpticalDiscDrive_SlimDrive_SN_S
082D.asp?pageSpecifications 11
ftp//download.intel.com/design/Pentium4/manuals/2
4896606.pdf 12 http//www.pricewatch.com/
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