Sequential Circuits

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Sequential Circuits
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Topics

• Sequential Circuits
• Latches
• Flip Flops

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Sequential Circuits

• State of system is stored information
• Present state and inputs, determine outputs and
  next state

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Types of Sequential Circuits

• Synchronous
• State changes are synchronized by one or more
  clocks
• Asynchronous
• Each state change occurs independently of other
  changes

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Clocking of Synchronous

• Changes of the state enabled by a clock

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Comparison

• Synchronous
• Easier to analyze because gate delays can be
  factored out
• Choose the clock so that changes are only allowed
  to occur before next clock pulse
• Asynchronous
• Potentially faster
• Harder to analyze
• Will look mostly at synchronous

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Basic Storage

• Apply low or high for longer than tpd
• Feedback will hold the value of the input

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SR (set-reset) Latches

• Basic storage made from gates
• Requirement outputs be the complements of each
  other

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Simulation Of SR Behavior
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Latch

• Similar made from NANDs

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Add Control Input

• Gates when state can change
• Is there a latch with no undefined state?

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D-type Latch

• No undefined (illegal) state

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Transparency

• As long as C (the trigger ) is high, state can
  change
• This is called transparency
• Problem with transparency
• Because of transparency output of one latch may
  feedback
• So more state changes than desired may happen
• Want to change latch state once
• Depending on inputs at time of clock

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Effects of Transparency

• Because of transparency output of one latch may
  feedback
• So more state changes than desired may happen
• Depends on gate delays
• Want to change latch state once
• Depending on inputs at time of clock

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Flip-Flops

• Two major types
• Master-Slave
• Two stage
• Output not changed until clock disabled
• Edge triggered
• Change happens when clock level changes

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Master-Slave Flip-Flop

• Either master or slave is enabled, not both

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Timing Diagram
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Note

• Output no longer transparent
• New inputs appear at latches are not sent to
  output until clock low
• Changes at input of FF when clock high trigger
  next state
• As the clock get faster, more problems are
  possible
• Have to guarantee circuit settles while clock low