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PPT – 332:578 Deep Submicron VLSI Design Lecture 3 Deep Sub-micron MOS Transistor Theory PowerPoint presentation | free to download - id: 41b6e9-YjYwZ

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332578 Deep SubmicronVLSI DesignLecture

3Deep Sub-micron MOS Transistor Theory

Material from Low-Power CMOS VLSI Circuit

Design By Kaushik Roy and Sharat C. Prasad

- Michael L. Bushnell -- CAIP Center and WINLAB
- ECE Dept., Rutgers U., Piscataway, NJ

Outline

- Deep Sub-micron Transistor Models
- Subthreshold current and subthreshold swing
- Drain Induced Barrier Lowering (DIBL)
- Punchthrough
- Gate Induced Drain Leakage (GIDL)
- Summary

Deep Sub-Micron Threshold Equations

Motivation for Transistor Review

- Reformulate MOSFET models and equations to
- Obtain better VT computation
- Obtain critical subthreshold current
- Obtain critical subthreshold swing
- Calculate drain induced barrier lowering (DIBL)
- Allows correct estimation and understanding of

low-power currents

Definitions

- Eg is Band gap energy of semiconductor in eV (1.1

eV for Si) - Ei is intrinsic energy level in undoped

semiconductor (halfway through band gap) - Ec is energy at bottom of conduction band
- Ev is energy at top of valence band
- EF - q ?F is the average energy (Fermi level)

in conductor - VT is transistor threshold
- d is insulator thickness
- ?B is potential difference between Ei and EF

Ideal MIS Diode

- Type p semiconductor
- At V 0,
- fms energy

difference between

metal semiconductor - c semiconductor

electron affinity - fms fm (c ?B ) 0
- Flat-band condition usually have to apply VFB

(flat-band voltage) to cause this to happen

Eg 2q

Definitions

- po is hole concentration in semiconductor in

equilibrium - pp is hole concentration in semiconductor p side

of junction - np is e- concentration in semiconductor in

equilibrium - ni is intrinsic carrier concentration in undoped

semiconductor of both holes and e- - k is Boltzmanns constant
- T is absolute temperature in degrees Kelvin
- NA is acceptor concentration
- ND is donor concentration
- es is dielectric constant of Si
- b q / kT (reciprocal of thermal voltage)
- E is the electric field
- d is depletion region depth

Accumulation

(Ei EF) / kT

- p0 ni e
- Energy bands when a negative voltage is applied

Weak Inversion

- Energy bands when small positive bias voltage is

applied

Strong Inversion

- Ei at surface now below EF by 2 ?B fS
- ?B or ?B bulk potential difference between EF

and Ei - VT voltage necessary to cause strong inversion

Surface Space Charge and VT

- Charge sheet model
- Poisson equation
- D r (x, y, z)
- D es E (disp. Vector)
- r (x, y, z) total electric charge density
- Neglect fringing fields at edge of transistor, so

E is normal to SiO2 insulator

D

Derivation of Bulk Charge

Problem

- Next slides introduce the conventional VT

derivation and model - Problem Simply does not work any more for l lt

0.35 mm due to - Much greater sub-threshold current, which is due

to carriers diffusing in the channel before VGS

exceeds VT - VT no longer behaves the way the conventional

model predicts - Less susceptible to body effect
- Much more susceptible to VD (drain voltage) due

to drain-induced barrier lowering (DIBL) - Much more susceptible to gate-induced drain

leakage (GIDL) - Forced the adoption of a radically different

transistor model - Will give a new, corrected model later
- Models DIBL, GIDL, VT correctly using

curve-fitting to measurements

Conventional VT Derivation

- From Gausss Law, total charge in semiconductor

is

- Note fs surface potential 2 fB at strong

inv. - b q / kT, d SiO2 insulator thickness
- Ci insulator capacitance, ?i insulator

permittivity

Depletion Region Depth

- Depletion assumption regard depletion layer as

totally devoid of mobile charges - One-sided abrupt-junction assumption carrier

concentrations abruptly change to their intrinsic

values at distance W ( depletion region depth)

beneath surface - QT total trapped charge at semiconductor-insulat

or boundary

Flat-Band Voltage and Depletion Layer Depth

- Poisson equation (used to compute depletion layer

depth)

Depletion Layer Depth Wm at Strong Inversion

Inversion Layer Charge

- Qi inversion layer charge
- Qd depletion layer charge
- Qs surface charge

Inversion Layer Charge

Inversion Layer Thickness ti

Long-Channel MOSFETBody Effect

- VGS VGB VBS
- Surface potential was fs, becomes fS VBS

relative to source - VT now becomes (relative to source)

Subthreshold Current New Problem

- Weak inversion variation of minority carrier

concentration along channel

Subthreshold Current (contd)

- Consider grounded nFET source, VGS lt VT,

V DS 0.1 V - Weak inversion VDS drop almost entirely across

reverse-biased substrate-drain p-n junction - Small variation of fs along semiconductor surface
- y component Ey f / y is small
- Due to few mobile carriers and small Ey, drift

component of subthreshold ID,st negligible

Subthreshold Current (contd)

- Long channel allows the gradual channel

approximation to be used - np e
- np depends exponentially on fs, np (y)/ y can

be large - Diffusion current proportional to carrier

concentration gradient varies along y (distance

along channel)

bfs

ni2 NA

Terminology

- A channel cross-sectional area
- Dn electron diffusion coefficient
- Z channel width
- ti inversion layer thickness
- Qi ti q n (y) (per-unit inversion layer area

charge) - Equilibrium electron concentration
- Charge in inversion layer (weak inversion)

Derivation (Continued)

Source

Drain

Observation

- Different situation from MIS diode potential

gradient along y axis, must consider effect of

VDS - ID,st is the subthreshold component of drain

current

Subthreshold Current

- For long-channel MOSFET, subthreshold

drain-source current remains independent of

drain-source voltage - fs (y 0) varies exponentially with applied

gate voltage, so the drain-source current also

does - Independence of ID,st from VDS ceases when L is

as large as 2 mm when VDS is large enough to

merge source and drain depletion regions

(punchthrough) - Must prevent punchthrough, as it makes ID,st

independent of gate control voltage - Must keep punchthrough current smaller than ID,st

using implants

Subthreshold Swing

- Subthreshold swing is inverse of slope of log

ID,st vs. VGS - Cd gate depletion layer capacitance
- Ci insulator layer capacitance
- es permittivity of semiconductor
- ei permittivity of insulator
- d insulator thickness
- W depletion layer thickness
- Sst shows how effectively we can stop device

drain current flow when VGS goes below VT (units

of milliV/decade)

Subthreshold Swing (contd)

- Subthreshold swing (mV/decade) limits how small a

power supply we can use - For d 0, Sst 60 mV/decade (100 in

practice) - Due to non-zero oxide thickness and other factors
- Sst 100 reduces ID,st from 1 mA/mm at VGS VT

0.6 V to 1 pA/mm at VGS 0 V - Ways to make Sst smaller
- Thinner oxide layer to reduce d
- Lower substrate doping (larger W)
- Lower temperature
- Lower substrate bias

Submicron MOSFET

- Number of circuits on chip and their speed grow

exponentially - Make faster devices Increase ID,st (now drain

current in saturation) to charge/discharge

parasitic Cs faster - Was predicted that
- L 2 mm, VT would be independent of L, Z,

VDS - Instead, decreases with L, varies with Z (width),

decreases as VDS increases - Instead, VT increases less rapidly with VBS than

with longer channels - Need to understand these effects with small

dimension MOSFETs need to use curve-fitting to

model SPICE parameters

Submicron Effects on VT

- Short-channel-length effect
- VT decreases with decreasing L and increasing VDS
- Causes excessive leakage currents
- Can only achieve VT in 0.6 to 0.8 V range with

lightly doped substrate by using VT adjust

implants to increase surface doping - Lowers carrier mobility, subthreshold current,

etc. - When L same order of magnitude as width of

drain-substrate or substrate-source depletion

region - Ionic charge in these depletion regions reduces

charge needed by gate bias (added to total space

charge) to cause inversion - Smaller VGS turns on device
- Drain depletion area goes deeper into substrate,

making turn-on VT even smaller when

drainsubstrate reverse bias increases

Modeling Problems

- To understand this, must numerically solve

2-dimensional Poisson equation - Charge-sharing model considers channel charge to

be shared among source, gate, and drain, didnt

work - Drain-induced barrier lowering (DIBL) VT

decreases due to depletion region charges in

potential energy barrier between source and

semiconductor surface. - Reduces 2-dimensional Poisson equation to 1-D by

approximating 2f / x2 as a constant. Works

for L 0.8 mm and VDS as large as 3 V

Liu Model for DIBL

- Predicts short-channel threshold voltage shift

DVT,sc for deep submicron devices - Quasi-2D solution of 2D Poisson equation
- E has a horizontal component Ey (drain field) and

vertical component Ex (due to gate charge) - Ex maximal at source and decreases with y to a

minimum value at drain - Ex (x, y) value at insulator-semiconductor

surface is Ex (0,y) and goes to 0 at bottom edge

of depletion region - (Ex (W, y) 0)

DIBL Model

- Replace Ex/ x at each point (x,y) with its

average of values at (0, y) and (W, y) - Use depletion approximation, so depletion region

charge is simply the ionic charge (r (x, y) qNA)

DIBL (contd)

DIBL (contd)

- h is empirical fudge factor and W Wm at onset

of strong inversion - VsL VGS VT Effective gate voltage
- Vbi is built-in potential at drain-substrate and

substrate-source p-n junctions - Characteristic
- length
- Find DVT,sc by subtracting long-channel fs value

at VT from minimum of fs(y), using plotting and

curve fitting - Note that surface potential is never constant for

L 0.35 mm

Surface Potential Along Channel

Finding DVT

- Subtract minimum value of fs(y) from RHS of

Eq. (2.39) to get DVT,sc - If l gt 5L,
- Simplification
- Problem h makes it hard to find l (the

characteristic length)

Relating l to Lmin

- l can be related to minimum channel length Lmin

needed in a MOSFET to make it have long-channel

characteristics - If Lmin 4 l, then
- Leads to VT

Relating l to Lmin

- Note that Wj is the junction depth

Significant Changes in VT

- Need
- Then, for nFET with n poly gate
- For nFET with p poly gate
- Old VT equation becomes independent of VBS when

L lt 0.7mm

DIBL Concluded

- Dropped e term as being

negligibly small - For shorter channel lengths and higher drain

biases, - VT less sensitive to VBS than Eq. (2.49)

indicates - Instead, VT becomes completely independent of VBS

when - L 0.7 mm and for large values of VBS in all

cases

-2bfs-VBS

Narrow-Gate-Width Effects

- Have less effect on VT than short-channel effects
- View channel as rectangle in horizontal cross

section - First two effects caused by MOSFETs with raised

field-oxide isolation or semi-recessed local

oxidation (LOCOS) - 1st effect
- Parallel edges border drain and source, and

therefore are on depletion regions - Other two edges have no depletion region under

them - Charges under first 2 edges decrease charge

needed from gate voltage, so absence of depletion

region under other 2 edges increases VGS needed

to invert channel (increased VT)

Narrow-Gate-Width Effects

- 2nd Effect
- Higher channel doping along edges along width

dimension (due to channel stop dopants (nFET) or

oxidation of piled-up phosphorous (pFET) under

gate) - Need a higher VT to invert channel
- 3rd Effect
- Reverse short-channel effect As channel length

reduces from L 3 mm, VT initially increases

until L 0.7 mm. Below that, VT decreases

faster than predicted by theory - Caused by trench or fully-recessed isolation

when gate biased, field lines from gate region

overlapping channel are focused by edge geometry,

and make it easier to invert the channel

Overlapping Depletion Regions (or Punchthrough)

- As L decreases, separation between source and

drain depletion regions decreases - Increased reverse bias pushes boundaries further

from junction and closer to each other - Deep submicron MOSFET has a VT adjust implant

only at the surface. Causes greater expansion in

depletion regions below the surface, so

punchthrough first happens below the surface

Punchthrough

- Any drain voltage increase after punchthrough

happens lowers potential energy barrier for

majority carriers in the source - More of these enter the substrate, but some

collected by drain - Increases subthreshold current ID,st
- Slope of Sst curve flatter if subsurface

punchthrough occurred - Use VPT (punchthrough voltage) defined as value

of VDS where ID,st reaches some specific value

with VGS 0

Punchthrough (concluded)

- VPT is approximate value where

S

(source and drain depletion widths) L - NB bulk doping
- Very bad for low-power devices
- Fix with extra implants (cannot fix by changing

dopings alone)

Gate-Induced Drain Leakage

- Large field exists in oxide where n drain of

MOSFET lies under the gate and the drain is at

VDD, and the gate is at VSS - Causes a charge Qs eox Eox (Gausss Law) to be

induced in drain, sweeps any minority carriers

that are under the drain laterally to the

substrate - Enables tunneling in drain via a near-surface

trap, completes a path for a gate-induced drain

leakage (GIDL) current - Contributes to standby power, so must control

this by increasing oxide thickness, increasing

drain doping, or eliminating traps

Gate-Induced Drain Leakage

Summary

- Deep Sub-micron Transistor Models
- Need to use BSIMv3 V3.1 or BSIMv4 Berkeley models

for correct transistor simulation - Subthreshold current
- Drain Induced Barrier Lowering (DIBL)
- Gate Induced Drain Leakage (GIDL)
- Transistor avalanching
- Now necessary to correctly model fabrication line
- Conventional theory predicts parameters

incorrectly - VT is now less than predicted
- Body effect is less than predicted
- Leakage is much greater than predicted
- Must use BSIMv3 V3.1 or BSIMv4