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Introduction to CMOS VLSI Design Lecture 5: Logical Effort

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CMOS VLSI Design Lecture 5: Logical Effort GRECO-CIn-UFPE ... Which technology? Static CMOS Transmission gate Domino circuit Any other logic family Which topology? – PowerPoint PPT presentation

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Title: Introduction to CMOS VLSI Design Lecture 5: Logical Effort


1
Introduction toCMOS VLSIDesignLecture 5
Logical Effort
  • GRECO-CIn-UFPE

Harvey Mudd College Spring 2004
2
Outline
  • Introduction
  • Delay in a Logic Gate
  • Multistage Logic Networks
  • Choosing the Best Number of Stages
  • Example
  • Summary

3
Introduction
  • Chip designers face a bewildering array of
    choices
  • What is the best circuit topology for a function?
  • How many stages of logic give least delay?
  • How wide should the transistors be?
  • Logical effort is a method to make these
    decisions
  • Uses a simple model of delay
  • Allows back-of-the-envelope calculations
  • Helps make rapid comparisons between alternatives
  • Emphasizes remarkable symmetries

4
Logic effort
  • The method of Logical effort is a easy way to
    estimate delay in a CMOS circuit.
  • We can select the fastest candidate by comparing
    delay estimates of different logic structures.
  • The method can specify the proper number of logic
    stages.
  • The method allows a early evaluation of the
    design and provides a good starting point for
    further optimizations.

5
Chip design flow
6
Design levels
Technology independency
Technology dependency
Technology dependence
IBM
7
Circuit design styles
  • Custom design
  • Automatic design

8
Custom design flow
  • Additional human labor for better performance
  • - Designer has the flexibility to create cells at
    a transistor level
  • Or choose from a library of predefined cells.
  • Which technology?
  • Static CMOS
  • Transmission gate
  • Domino circuit
  • Any other logic family
  • Which topology?
  • NAND, NOR, INV or complex gates
  • Size transistors of the logic gates

9
Automatic design flow
  • This method uses synthesis tools to choose
    circuit topologies and gate sizes.
  • Synthesis takes much less time than manually
    optimizing paths and drawing schematics, but is
    generally restricted to a fixed library of static
    CMOS cell.
  • In general this method produces slower circuits
    than designed by a skilled designer.
  • Synthesized circuits are normally logically
    correct by construction, but timing verification
    is still necessary.
  • Performance can be improved by setting directives
    for synthesis tool in order to solve critical
    paths delay.

10
layout process
IBM
11
Layout process
LVS DRC Antenna
RC Resistance CAP Capacitance SDF
Standard Delay File
IBM
12
Delay estimate
  • The target her is design of fast chips.
  • Use a systematic approach to topology selection
    and gate sizing
  • A simple delay model thats fast and easy to
    use.
  • The delay model should be accurate enough that
    if it predicts
  • circuit a is significantly faster than
    circuit b, then circuit a
  • really is faster.
  • Delay model
  • Complexity of the gate
  • the load capacitance
  • parasitic capacitance.

13
Delay model
  • The delay model introduces a numeric path
    effort that allows the designer to compare two
    multistage topologies easily without sizing or
    simulation.
  • The model allows choosing the best number of
    stages of gates and for selecting each gate size
    in order to minimize delay.

14
Delay in a gate
  • The model describes delays caused by the
    capacitive load
  • that the logic gate drives and by the
    topology of the logic gate.
  • Clearly, as the load increases, the delay
    increases, but delay also depends on the logic
    function of the gate.

Slide 14
15
Delay in logic gates
Logic gates that compute other functions require
more transistors, some of which are connected in
series, making them poorer than inverters at
driving current.
A 2-input NAND gate
A NAND gate has more delay than a inverter
with similar transistor sizes that drives the
same load.
16
Delay in a Logic Gate
  • To model the delay if a logic gate
  • Firstly, to isolate the effects of a particular
    integrated circuit fabrication process by
    expressing all delays in terms of a basic unit ?
    particular to that process.
  • ? is the delay of an inverter driving an
    identical inverter with no parasitics.
  • Thus we express absolute delay as the product of
    a unitless delay of the gate d and the delay unit
    that characterizes a given process

17
Delay in a Logic Gate
  • Express delays in process-independent unit

t 3RC ? 12 ps in 180 nm process 40
ps in 0.6 mm process
18
Delay in a Logic Gate
  • Express delays in process-independent unit
  • Delay has two components

19
Delay in a Logic Gate
  • Express delays in process-independent unit
  • Delay has two components
  • Effort delay f gh (proportional to the load on
    the gates output)
  • Again has two components
  • The effort delay depends on the load and on
    properties of the logic gate driving the load.

20
Delay in a Logic Gate
  • Express delays in process-independent unit
  • Delay has two components
  • Effort delay f gh (related to gates load)
  • Again has two components
  • g logical effort (g is determined by gates
    structure)
  • g captures properties of the logic gate,
  • g ? 1 for inverter

21
Delay in a Logic Gate
  • Express delays in process-independent unit
  • Delay has two components
  • Effort delay f gh (related to gates load)
  • Again has two components
  • h electrical effort Cout / Cin
  • Ratio of output to input capacitance
  • Sometimes called fanout, h characterizes the load

22
Delay in a Logic Gate
  • Express delays in process-independent unit
  • Delay has two components
  • Parasitic delay p
  • Represents delay of gate driving no load
  • parasitic delays are given as multiples of the
    parasitic delay of an inverter.
  • A typical value for pinv is 1.0 delay units. pinv
    is a strong function of process-dependent
    diffusion capacitances.

d ghp
23
Logical effort
  • The delay formulation involves four parameters
  • The process parameter ? represents the speed of
    the basic transistors.
  • The parasitic delay p expresses the intrinsic
    delay of the gate due to its own internal
    capacitance, which is largely independent of the
    size of the transistors in the logic gate.
  • The electrical effort, h, combines the effects of
    external load, which establishes Cout , with the
    sizes of the transistors in the logic gate, which
    establish Cin.
  • The logical effort g expresses the effects of
    circuit topology on the delay free of
    considerations of loading or transistor size.
  • Thus, we can observe that logical effort is
    useful because it depends only on circuit
    topology.

24
Computing Logical Effort
  • DEF logical effort is how much more input
    capacitance a gate must present in order to
    deliver the same output current as an inverter.
    (Sutherland)
  • Measure from delay vs. fanout plots
  • Or estimate by counting transistor widths

Gates NAND e NOR with relative transistor widths
chosen for roughly equal output currents.
an inverter has a logical effort of 1.
g no.Cin/no.Cout
25
Example Inverter
  • Estimate inverter delay (reference)

2
2
1
1
26
Example 2-input NAND
  • Estimate 2-input NAND delay

27
Delay Plots
  • d f p
  • gh p

28
Delay Plots
  • d f p
  • gh p

29
Catalog of Gates
  • Logical effort of common gates

Gate type Number of inputs Number of inputs Number of inputs Number of inputs Number of inputs
Gate type 1 2 3 4 n
Inverter 1
NAND 4/3 5/3 6/3 (n2)/3
NOR 5/3 7/3 9/3 (2n1)/3
Tristate / mux 2 2 2 2 2
XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8
30
Example 8-input AND
31
Catalog of Gates
  • Parasitic delay of common gates
  • In multiples of pinv (?1)

Gate type Number of inputs Number of inputs Number of inputs Number of inputs Number of inputs
Gate type 1 2 3 4 n
Inverter 1
NAND 2 3 4 n
NOR 2 3 4 n
Tristate / mux 2 4 6 8 2n
XOR, XNOR 4 6 8
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