The ESW Paradigm

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The ESW Paradigm

• Manoj Franklin Guirndar S. Sohi
• 05/10/2002

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Observations

• Large exploitable ILP, theoretically
• Close instructions dependent parallelism
  possible further down stream
• Centralized resources is bad
• Minimizing comm cost is important

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What about others?

• Dataflow model
• most general
• unconventional PL paradigm
• comm cost can be high
• SS, VLIW (sequential)
• temporal locality
• large centralized HW
• compiler too dumb
• not scalable
• ESW dataflow sequential

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Design Goals

• Decentralized resources
• Minimize wasted execution
• Speculative memory address disambiguation
• realizability

Replace large dynamic window with many small ones
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How it works

• Basic window
• Single entry, loop-free, call-free block
• Equal, superset or subset of basic block
• Execute basic windows in parallel
• Multiple independent stages
• Complete with branch prediction, L1 cache, reg
  fileetc.

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Dist Inst Supply
Optimization Snooping on L2-L1 Cache traffic
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Dist Inter-Inst Comm

• Architecture
• dist. future file
• create/use masks for dep. check

• Observation
• Register use mostly within basic block
• The rest in subsequent blocks

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Dist DMem System

• Problem
• Addr. space large, cant create/use mask
• Need to maintain consistency between multiple
  copies
• Solution ARB

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ARB

• - Bits cleared upon commit
• Restart stages when dependency violated
• When load, forward values from ARB if already
  exists

Q. What happens when ARBs full?
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Simulation Environment

• Custom simulator using MIPS R2000 pipeline
• Up to 2 inst fetch/decode/issued/ per IE
• Up to 32 inst per basic window
• 4K word L1 cache, 64KB L2 DM Cache (100 hit
  rate, what??)
• 3-bit counter branch prediction

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Results

• Optimizations
• Moving up instruction
• Expand basic window (in eqntott and expresso)

Basic window lt basic block
But is 100 cache hit rate reasonable?
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Discussion

• Compare this to CMP? RAW?
• Does the trade-off strike a balance?

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New Results (1)
In order execution
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New Results (2)
Out of order execution