High-Level%20Synthesis%20an%20introduction

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High-Level Synthesisan introduction
Prof. Jan Madsen Informatics and Mathematical
Modelling Technical University of Denmark Richard
Petersens Plads, Building 321 DK2800 Lyngby,
Denmark
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Hardware synthesis

• Starts from an abstract behavioral description
• Generates an RTL description
• Need to restrict the target hardware otherwise
  search space is too large

P1
P2
P3
ASIC
CPU
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Hardware synthesis

• How is the behavior specified?
• Natural languages
• C/C
• VHDL/Verilog
• What is the target architecture of the ASIC?

P1
P2
P3
ASIC
CPU
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Hardware model - components

• Most synthesis systems are targeted towards
  synchronous hardware
• Functional units
• Can perform one or more computations
• Addition, multiplication, comparison, ALU, etc.
• Registers
• Store inputs, intermediate results and outputs
• May be organized as a register file

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Hardware model - interconnection

• Multiplexers
• Select one output from several inputs
• Busses
• Connection shared between several components
• Only one component can write data at a specific
  time
• Exclusive writing may be controlled by tri-state
  drivers

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Hardware model parameters

• Clocking strategy
• Single or multiple phase clocks
• Interconnect
• Allowing or disallowing busses
• Clocking of functional units
• Multicycle operations
• Chaining
• Pipelined units

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Hardware model example
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Hardware concepts

• Data path
• Network of functional units, registers,
  multiplexers and buses
• Control
• Takes care of having the data present at the
  right place at a specific time
• Takes care of presenting the right instructions
  to a programmable unit
• Often high-level synthsis concentrates on data
  path synthesis

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Methodology
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Input format

• Input
• Behavior described in textual form
• Conventional programming language
• Hardware description language (HDL)
• Has to be parsed and transformed into an internal
  representation
• Conventional compiler techniques are used

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Internal representation

• Data-flow graph (DFG)
• Used by most systems
• May or may not contain information on control flow

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Data flow
x a b y c d z x y
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DFG semantics


x
y
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Exercise 1 data flow graph of DiffEq

• Solve the second order differential equation
• y 3zy 3y 0
• Iterative solution

While (zlta) z1 z dz u1 u
(3zudz) (3ydz) y1 y (udz) z
z1 u u1 y y1
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Exercise 1 - result
u
dz
z
y
u
dz
z
dz
3
3

u1
y1
ctrl
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High-level synthesis
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High-level synthesis

• Scheduling
• Determine for each operation the time at which it
  should be performed such that no precedence
  contraint is violated
• Allocation
• Specify the hardware resources that will be
  necessary
• Assignment
• Provide a mapping from each operation to a
  specific functional unit and from each variable
  to a register

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High-level synthesis

• Scheduling, allocation and assignment are
  strongly interrelated
• But are often solved separately!
• Scheduling is NP-complete heuristics have to be
  used!

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Scheduling

• Input
• DFG G(V, E)
• Library of ressource types R
• Mapping
• a V g R, a(vi ) r
• a given operation may be mapped to different
  ressource type, e.g. may be performed by an
  adder or an ALU
• execution delay d(vi ) di
• ressource type cost w(r)

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Scheduling

• Start time of operations
• T ti i 0, 1, , n
• Scheduling is the task of determining the start
  times subject to the precedence constraints of
  the DFG
• s V g Z
• s(vi ) ti such that ti ? tj dj, ? i, j
  (vj, vi ) ? E
• Latency l tn t0
• Cost of schedule Sr? R w(r) Nr(s)

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Scheduling
Mathematical domain
Scheduling algorithm
synthesis
specification
implementation
DFG
Scheduled DFG
C program
implementation
specification
Physical domain
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Scheduling ASAP

• Map operations to their earliest possible start
  time not violating the precedence constraints
• Easy and fast to compute
• Find longest path in a directed acyclic graph
• No attemp to optimize ressource cost
• Gives the fastest possible schedule if unlimited
  amount of resources are available
• Gives an upper bound on execution speed

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ASAP algorithm
For each node vi ? V do if pred(vi) Ø then
Ei 1 V V vi else Ei 0
endif endfor
While V ? Ø do for each node vi ? V do if
all_sched(pred(vi),E) then Ei
max(pred(vi),E) 1 V V vi
endif endfor endwhile
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DiffEq
u
dz
z
y
z
dz
u
dz
3
3

u1
y1
ctrl
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Exercise 2 latency and resources

• Assume
• cycle time 25 ns
• d, d, d-, dlt 25 ns
• What is the latency of the schedule?
• How many resources are needed?
• How many resources are needed, if we introduce an
  ALU (,-,lt)
• What is the latency if we have only 1 multiplier?
• What is the latency if
• d 25ns and dALU 12ns

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Exercise 2 result

• What is the latency of the schedule?
• 425ns 100ns
• How many resources are needed?
• 4, 1, 1-, 1lt
• How many resources are needed, if we introduce an
  ALU (,-,lt)
• 4, 2ALU
• What is the latency if we have only 1 multiplier?
• 725ns 175ns
• What is the latency if
• d 25ns and dALU 12ns
• 325ns 75ns (operator chaining)

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Scheduling - ALAP
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Scheduling ALAP

• Map operations to their latest possible start
  time not violating the precedence constraints
• Needs a latency constraint
• Easy and fast to compute
• Find longest path in a directed acyclic graph
• No attemp to optimize ressource cost

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Scheduling ASAP / ALAP

• Are ASAP and ALAP useful?
• sASAP (vi ) Ei
• sALAP (vi ) Li
• Operator flexibility Li Ei
• Also known as mobility
• Mobility 0
• operator has to be scheduled at Ei
• otherwise latency constraint is violated
• Mobility gt 0 gives scheduling freedom

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Scheduling list based

• Generalization of ASAP
• Priority-list of ready nodes
• A ready node is an operator that has all
  predecessors already scheduled
• The priority-list is always sorted with respect
  to a priority function

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List scheduling algorithm
ins_ready_ops(V,PListr1, PListr2,,
PListrm) Cstep 0 While ((PListr1 ? Ø) or or
((PListrm? Ø)) do Cstep Cstep 1 for k
1 to m do for funit 1 to Nk do if
PListrk ? Ø then schdule_op(first(Plistrk)
,Cstep) Plistrk delete(Plistrk,first(Pl
istrk)) endif endfor endfor
ins_ready_ops(V,PListr1, PListr2,,
PListrm) endwhile
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DiffEq
u
dz
z
y
z
dz
u
dz
3
3
e,c,d
Plist
a,b,c,d
c,d
f,d

Plist
j
Ø
Plist-
Ø
g
Ø
k
Plistlt
Ø
u1
y1
ctrl
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List scheduling

• Priority may be based on other measures than
  mobility
• Length of longest path to a node with no
  immediate successor
• Number of immediate successor nodes
• High number means high priority