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Focus Group 8 GALS: the role of globally asynchronous, locally synchronous systems in the future des

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Focus Group 8 ... GALS Focus Group 8, IWLS 2002. 2. Participants (alphabetical order) Iris Bahar, Brown U. ... GALS Focus Group 8, IWLS 2002. 8. System ... – PowerPoint PPT presentation

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Title: Focus Group 8 GALS: the role of globally asynchronous, locally synchronous systems in the future des


1
Focus Group 8GALS the role of globally
asynchronous, locally synchronous systems in the
future design flow
Title Goes Here
2
Participants (alphabetical order)
  • Iris Bahar, Brown U.
  • Bob Brayton, U.C. Berkeley
  • Tiberiu Chelcea, Columbia U.
  • Philip Chong, U.C. Berkeley
  • Jordi Cortadella, Universitat Politecnica
    Catalunya
  • Duc Anh Vu Dinh, TIMA
  • Masanori Hashimoto, Kyoto U.
  • Soha Hassoun, Tufts U.
  • Feipei Lai, Natl. Taiwan U.
  • Diana Marculescu, CMU
  • Steve Nowick, Columbia U.
  • Hiroshi Saito, U. of Tokyo
  • Herman Schmit, CMU
  • Ellen Sentovich, Cadence Berkeley

3
Questions
  • Motivation Why GALS?
  • Challenges
  • Ahead Opportunities for the future

4
Why GALS?
  • Why not LAGS Locally Asynchronous, Globally
    Synchronous systems?
  • Decided well stick with GALS (at least sounds
    better ?)
  • Driving factors for using GALS
  • SoC IP reuse and design productivity IP cores
    from different vendors may be optimized for
    various speeds
  • Design effort and performance more and more
    difficult to drive a global clock signal across a
    large area, with minimal clock skew
  • Need for fine-grain adaptability of workload
    dependent applications (lower power at same
    performance) different speeds/voltages for each
    synchronous island

5
Challenges
  • Metastability problems appear whenever crossing
    timing domains or async-sync (async-async)
    boundaries
  • Performance evaluation how can it be done?
  • Performance metrics which are the best metrics
    to characterize and cross-compare various
    implementations?
  • Partitioning for applications that are
    motivated by costly global clock distribution,
    and not by IP-reuse (e.g., complex, high
    performance processors)
  • Local clock generation

6
Metastability - Solutions
  • Synchronizers modular interface circuits
    assume the use of at least 2-3 FFs
  • Pro Simple, no throughput degradation
  • Con Latency increase
  • Mixed timing FIFOs - Tolerate larger difference
    in speed of producer/consumer local speeds
  • Stretchable clocks the receiver local clock is
    stopped or stretched until the right timing
    condition is satisfied
  • Pro Lower performance penalty, clocks are
    stopped infrequently
  • Con No external clock controlability,
    interfering with the local clocking of the
    receiver

7
Performance Evaluation
  • At system level, various synchronous islands
    can be viewed as asynchronous or synchronous for
    performance evaluation purposes
  • Simulation?
  • State-of-the-art in industry
  • Slow, but accurate
  • Analytical methods
  • Reuse existing knowledge from classic networking?
  • Queueing Theory, Process Algebra
  • Possible less complexity (100s of synchronous
    islands)
  • Reuse existing knowledge from asynchronous
    performance evaluation?
  • Markov Chains, Petri Nets, Free-Choice Petri Nets
  • Problem network traffic may not be distributed
    nicely
  • Need precharacterization or profiling
  • Faster, but less accurate
  • Depends on the error tolerance and run-time
    requirements

8
System Performance Metrics
  • Latency
  • End-to-end latency
  • Need to anaylze the effect of asynchronous
    communication scheme
  • Impact of clocking less area less clock skew,
    possibly higher local clock speed
  • Need to include effects of process variation due
    to temperature, clocked memory elements, etc.
    very difficult, these are very much related to
    physical parameters
  • Average vs. worst case analysis
  • Both are important
  • Need to have bounds on synchronous computation
    latency, as well as distributions
  • Buffer sizing
  • State-of-the-art overdesign so as overflow,
    performance reduction, deadlock or packet
    dropping doesnt happen
  • Need tools for automatic determining the buffer
    size

9
Partitioning
  • In case of IP-based SoC design, partitioning is
    already done
  • But in case of other applications (e.g. complex
    processors, C or C specifications), its not
  • What is the role of physical constraints?
  • Use of placement info
  • Number of cycles needed to communicate among
    physically close or far apart synchronous
    islands
  • Communication traffic
  • Different communication schemes for different
    types of traffic
  • Used in conjunction with physical placement
    information

10
Local Clock Generation
  • Ring oscillators
  • Pro Simple
  • Con Cannot be controlled externally
  • Local PLLs
  • Pro Externally controlled
  • Con More costly
  • But they scale

11
Opportunities Ahead
  • Enable IP-reuse, increase design productivity,
    shorten time-to-market
  • Enable fine-grain adaptability for workload
    dependent applications
  • E.g., network processors, high-end computing,
    media applications
  • Each synchronous island can run at varying
    speeds and voltages for better adaptability and
    lower power consumption

12
Thank you!
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