Future Prospects for Moore

1
Future Prospectsfor Moores Law
Eighth Annual High Performance Embedded Computing
Workshop Lincoln Laboratory September 28,
2004 Robert Doering Texas Instruments, Inc.
2
Generalizations of Moores Law

• Exponential trends in
• More functions per chip
• Increased performance
• Reduced energy per operation
• Decreased cost per function (the principal
  driver)
• transistors, bits, etc.

Price per Transistor in MPU ()
1
-2
10
-4
10
Dollars to Microcents
Source DataQuest, Intel
3
High-Level CMOS Technology Metrics What are the
Limits ?

• Component Diversity (integrated logic, memory,
  analog, RF, )
• Cost/Component (e.g., µ/gate or µ/bit in an IC)
• Component Density (e.g., gates/cm2 or bits/cm2)
• Logic Gate Delay (time for a gate to switch logic
  states)
• Energy Efficiency (energy/switch and energy/time)
• Mfg. Cycle Time (determines time-to-market for
  new designs as well as rate of yield learning)
• All of these are limited by multiple factors
  inter-linked into a complex tradeoff space. We
  can only touch on a few of the issues today !

4
State-of-the-Art CMOS in 2004

• ITRS Technology Node 90 nm (half-pitch of
  DRAM metal lines)
• 4T-Gates/cm2 37x106 (150 million
  transistors/cm2)
• 6T-eSRAM bits/cm2 108 (600
  million transistors/cm2)
• Cost/Gate (4T) 40 µ (high volume chip
  area 1 cm2)
• Cost/eSRAM bit 10 µ (high volume chip
  area 1 cm2)
• Gate Delay 24 ps (for 2-input, F.O. 3
  NAND)
• Switching Energy 0.5 fJ (for inverter,
  half-cycle)
• Passive Power 6 nW (per minimum-size
  transistor)
• Min. Mfg. Cycle Time 10 days (or 3 mask
  levels/day)
• Values at extreme tradeoff for MPU application

5
Scaling -- Traditional Enabler of Moores Law
500
return to 0.7x/3-yr ?
350
250
180
ITRS Lithography Half-Pitch (DRAM)
130
90
65

Feature Size nm
45

32
22
ITRS Gate Length
13
Year of Production
9
For Speed, Low-Cost, Low-Power, etc.
6
Can We Extendthe Recent 0.7x/2-year Litho
Scaling Trend ?
104
Abovewavelength
Nearwavelength
Belowwavelength
1500
3000
2000
1000
103
DUVl248nm
500
600
193l193nm
157l157nm
g-linel436nm
400
350
i-193l133nm
Half-Pitch / Wavelength (nm)
250
130
i-linel365nm
180
102
90
65
45
32
l EUV 13.5nm
101
1980
1990
2000
2010
Year of Production
For lithography, its a question of cost and
control/parametric-yield !
7
A Bag of Tricks for Optical-Extension
0.25
Custom
Illumination mode Other (Tool) Mask Mask
OPC Resist
k1
Scattering bars
Dipole
Alternating PSM
Focus drilling
Quasar
Hammerheads
Strength of enhancement



Complexity (mask, use)
Soft Quasar
Phase filters

Attenuated PSM 18
Serifs
Thin resist
Double Exposures
Annular
Attenuated PSM 6
NA

Line Biasing
0.5
Thick resist
Conventional
Binary Intensity Mask
Wavelength
Source ASML
Of course increasing complexity ? increasing
cost !
8
Amortization of Mask Cost _at_ 130nm
Significant motivation for some form of
mask-less lithography !
1 million units required to get within 10 of
asymptotic cost ! (and getting worse with
continued scaling)
9
Of course, overall scaling is limitedby more
than just lithography !

• Growing Significance of Non-Ideal
  Device-Scaling Effects
• ION vs. IOFF tradeoff
• unfavorable r and L scaling for interconnects
• Approaching Limits of Materials Properties
• Heat removal and temperature tolerance
• CMAX vs. leakage tradeoff for gate dielectric
• CMIN vs. mechanical-integrity tradeoff for
  inter-metal dielectric
• Increases in Manufacturing Complexity/Control
  Requirements
• cost and yield of increasingly complex process
  flows
• metrology and control of LGATE, TOX, doping,
  etc.
• Affordability of RD Costs
• development of more complex and near cliff
  technologies
• design of more complex circuits with less
  ideal elements

10
ITRS Tries to Address Top-Down Goals
2003
2001
MPU Clock (GHz)
11
ITRS Highlights Scaling Barriers, e.g.
Production Year 2001 2004 2007 2010 2013 2016 Lit
ho Half-Pitch nm 130 90 65 45 32 22 Overla
y Control nm 45 32 23 18 13 9 Gate Length
nm 65 37 25 18 13 9 CD Control
nm 6.3 3.3 2.2 1.6 1.2 0.8 TOX
(equivalent) nm 1.3-1.6 1.2 0.9 0.7 0.6 0.5
IGATE (LMIN) µA/µm - 0.17 0.23 0.33 1 1.6
7 ION (NMOS) µA/µm 900 1110 1510 1900 2050
2400 IOFF (NMOS) µA/µm 0.01 0.05 0.07 0.1
0.3 0.5 Interconnect KEFF - 3.1-3.6 2.7-3.0 2.
3-2.6 2.0-2.4 lt2.0
12
Another Interconnect-Scaling Issue
Wire width lt mean-free-path of electrons
5
p0
Surface scattering becomes dominant p0 (diffuse
scattering) p1 (specular scattering)
4
3
Resistivity(µOcm)
2
p0.5
1
0
0
100
200
300
400
500
Metal Line Width (nm)
13
2004 LG 37-nm Transistor
TOX(equiv.) 1.2 nm
14
Can Some Hi-K Dielectric Replace SiON ?

• Sub-nm SiON
• mobility
• uniformity
• leakage

Source Intel
15
In general, continued transistor scalingrequires
new materials, processes,
Ni-silicide process for low resistance at short
gate lengths (near term)
Selective-epi raised source/drain for shallow
junctions reduced short-channel effects
Metal gate electrode to reduce gate depletion
High-k gate dielectric for reducing gate current
with thin Tox
GATE
Etches for new materials that achieve profile,
CD control, and selectivity
DRAIN
SOURCE
STI
STI
Halo I2
P-WELL
Doping and annealing techniques for shallow
abrupt junctions
Strained channel for improved mobility
Si-Substrate
16
and, eventually new structures
Steps toward ideal coax gate ?
17
Potential FET Enhancements ?
Calculations by T. Skotnicki
18
At PQE 2004, Professor Mark Lundstrom expressed
the outlookSub-10nm MOSFETs will operate, but
- on-currents will be 0.5xIballistic,
off-currents high, - 2D electrostatics will be
hard to control, - parasitic resistance will
degrade performance, - device to device
variations will be large, and - ultra-thin
bodies and hyper-abrupt junctions will be
essential
19
ITRS Assessment of Some Current Ideas for
Successors to CMOS Transistors
No obvious candidates yet for a CMOS replacement !
20
SRC Research Gap Analysis (for lt50nm)
New Tasks 372M
Worldwide Funding 1,386 M
Asia-Pacific 103 M
Government Funding
Ongoing Tasks 2,169M
21
ITRS Emerging Technologies ?
Another Dimension
? Extending Moores Law via Integrating New
Functions onto CMOS
22
Why Moores Law Is Still a Fun Topic !
A 1975 IC Technology Roadmap
What makes us think that we can forecast more
than 5 years of future IC technology any better
today ?!!