Design Better

1

• Design Better
• Debug Faster
• Novas
• DAC 2002

2
Introduction

• Complexity
• Complex designs are hard to understand
• Understanding
• Understanding is required for successful design
  and debug
• Technology
• Debug technology improves understanding
• Design better, debug faster
• Novas
• Delivers an expanding range of debug technology
  and products

3
Complexity

• Many reasons for complexity
• Large chip, large team
• High-performance design tactics
• Outside IP, many languages, many tools
• Impact of complexity
• Lack of understanding, long debug
• Constant interruptions of most knowledgeable
  people
• Risk of missed schedules

4
Verification Debug
Verification Process
Testbench
Capture
Intent
Verilog
VHDL
Detect
Capture
Change Code
Simulate Again
Errors
Design
Debug Process
Debug
Verification
Understand design
Locate/isolatecauses effects
Modify design
Understand design
5
Debug Understanding Design Behavior

• Static structural
• Blocks, ports, signals
• Hierarchy, connectivity
• Dynamic temporal
• Localized cause-and-effect relationships
• Operation of key functions over time
• Other parts of the process require understanding
• Integration of unfamiliar blocks
• Writing testbench and property code
• Investigating synthesis results
• Optimizing timing paths
• Making late-stage netlist changes (ECOs)

6
Economics of Understanding

• Direct cost
• Up to 50 of engineers time
• Figuring out how designs work or why they dont
• 30,000 to 100,000/engineer/year
• Opportunity cost
• Project schedule
• Prevents writing more tests
• Delays work on the next design

7
Debug History
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Stop at simulation time 146000
Stop at simulation time 146000
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1
1
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c24gt 20
1980s
1990s
1980s
1990s
Pre 1980
2000s
Pre 1980
2000s
Waveforms
Debug System
Oscilloscope, Logic analyzer
Simulator(command line)
8
Baseline System Requirements

• Independence
• Use standalone or in conjunction with detection
  tools throughout the flow
• Interoperability
• Open interfaces and integration with simulators
  and other detection tools
• Data Model
• Optimized for design exploration and debug
• Visualization and analysis
• Wide variety of integrated tools for exploring
  the design from many angles
• Languages
• Complete support for Verilog, VHDL, and
  mixed-language descriptions
• Abstractions
• Support for gate-level netlists, RTL, and
  system-level abstractions
• Scalability
• Architecture designed to track designs as they
  grow 1000x over 15 years

9
Emerging Challenges

• Existing debug technologies and methods are
  reaching their limit
• Reliance on structural analysis limits ability to
  quickly grasp complex functionality and
  cause-and-effect relationships
• New verification methods demand more from a debug
  system
• Support for HVLs, properties, and assertions
• Design reuse and sharing makes it increasingly
  difficult to understand the design under test
• Need new ways to capture, preserve, and share
  engineers knowledge across distance and time

10
Two Ways to Improve Understanding

• Better ways to figure out how designs work and
  why they dont
• Reverse engineer the knowledge
• Better ways to capture knowledge and reuse it
• Engineer in the knowledge

11
Novas

• Mission engineering productivity through design
  understanding
• Technologies and tools to debug, explore, and
  understand complex and unfamiliar designs
• Advanced technology system architecture
• Focused on design exploration, debug, and
  understanding
• Expanding line of sophisticated debug products
• Debussy? Industry-leading HDL debug system
• Verdi Next-generation behavior-based debug
  system
• Open systems
• Fully interoperable with leading verification
  tools
• Easy to integrate with in-house tools

12
Industry Partners

• HD Lab (Japan)
• IKOS Systems
• Incentia Design Systems
• InnoLogic Systems
• Mentor Graphics
• Model Technology
• Nassda Corporation
• Real Intent
• Simpod
• Silicon Design Validation
• Synopsys
• SynTest Technologies
• Tharas Systems
• TransEDA
• Verisity
• Verplex Systems

• 0-In Design Automation
• Aldec
• Antrim Design Systems
• Avant!
• Averant
• Avery Design Systems
• Axis Systems
• Cadence
• Quickturn
• Silicon Perspective Corporation
• Celestry
• Co-Design
• CoWare
• Denali Software
• EverCAD
• Fintronic USA
• Forte Design Systems

13
Design Knowledge Architecture
KDB
ExtractDesign Knowledge
Knowledge Engine Compilers
ConnectUser Knowledge
Understand
Design BetterDebug Faster
APIs
Capture Verification Knowledge
FSDB
14
Expanding Debug Technology
Active Knowledge
System Level
Behavior-Based
Waveforms
Debussy
Verdi
15
DebussyKnowledge-Based Debug System

• Core modules
• nTrace
• Hyperlinked source code tracing and analysis
• nSchema
• Logic diagramgeneration analysis
• nState
• Finite State Machine visualization analysis
• nWave
• State of the art waveform viewing analysis

• Complementary products
• nECO
• Netlist-level ECOs
• nLint
• HDL rule checking
• nCompare
• Simulation dump file comparison

Provides platform base technologyfor other
Novas systems
16
Behavior-Based Debug

• Challenge As design complexity increases,
  structural debug techniques run out of steam
• Novas Technology Solution
• Rigorous analysis to extract design behavior
• Analyzes cause-effect relationships
• Identifies control/data-path, active/non-active
  fanins
• Temporal visualization to display design behavior
  over time
• Register flow graph
• Statement flow graph
• Symbolic analysis engines to explore alternate
  design behavior
• What-if analysis
• RTL changes

17
VerdiBehavior-Based Debug System

• Built on Design Knowledge Architecture
• Compilers, databases, interfaces
• Interoperability
• Incorporates Debussy core functions
• Structural exploration and analysis
• Source tracing, waveforms, schematics, FSMs
• Practical application of powerful new technology
• Behavior analysis
• Identifies control and data paths
• Locates and isolates active paths
• Temporal visualization
• Displays cause and effect relationships
• Register flow graph, statement flow graph
• Symbolic exploration
• Evaluates alternate behavior during debug
• Symbolic analysis what-if

I1
5
1
0
1
5
5
0
0
1
R1
5
3
2
1
S1
100
90
80
70
18
Expanded Architecture
Novas Design Knowledge Architecture
KDB
Temporal Visualization Automated Tracing Symbolic
Analysis
Design Data
Trace
HDL
Behavior
SDB
Analysis
Source Code Waveforms Schematics FSMs
Testbench
Simulation
FSDB
Debug Tools
SDB Symbolic databaseKDB Knowledge
databaseFSDB Fast signal database
19
Behavior Analysis

• Builds an internal model of design behavior using
  synthesis technology
• Equations Each signal value at a specific point
  in time is expressed as a function of other
  signal values at specific points in time
• Differentiates data from control signals
• Uses simulation results
• Determine clocking
• Prune inactive elements

20
Temporal Visualization
Register flow graph
time
Statement flow graph
21
Tracing Causes Effects

• Unrolls design functions over time
• Automatically locates actual causes of specific
  values

Clk3_at_700
Clk2_at_725
Clk3_at_800
In1_at_780
ACC
20
IDR
ACC
55
55
CWR
3
800
725
700
time
22
Exploration What-if
R1100 f((5,1,0,1,3,S1)70, (I1,5,0,1)80,
(0,5)100)

• Solves equation in terms of variables to achieve
  desired output value
• If (R13)100, (S1?)70 and (I1?)80
• Propagates modified values to display effect on
  operation
• If (S14)70 and (I10)80, (R1?)100

23
Debug System Operation

• Compiles HDL design from original source
• Captures design intent and knowledge
• Recognizes key structures
• Flops and latches
• Extracts temporal design behavior
• Symbolic representation, data and control
• Isolates elements critical to task at hand
• Related signals, partial schematics
• Design behavior unrolled across several cycles in
  flow graphs
• Guides user to cause of problem
• Cause of transition, active drivers
• Origin of value
• Evaluates potential fixes
• What if I change the values of these signals at
  times 70 and 80?
• How can I get this signal value at time 100?
• Minimizes compute and storage requirements

24
Application Examples

• Understand unfamiliar code
• Debug RTL simulation results
• Isolate and investigate a critical timing path
• Gate-level netlist changes

25
Understand Unfamiliar Code

• Problems
• Which components are connected?
• What are the drivers/loads of this signal?
• Where is the definition of this component?
• What logic affects this signal over time?
• How can the FSM get into this state?
• Debussy and Verdi solution
• Integrated, interactive, synchronized views
• Hierarchy, source, logic bubble diagrams
• Register and statement flow graphs
• Click signal to find drivers and loads,
• Click instance to find definition
• Easily discover investigate related logic
• Flat logic diagram showing fanin/fanout cone
• Register flow graph showing operation over
  several cycles

26
Debug RTL Simulation Results

• Problems
• Wrong values, bad transitions
• Too many signals, files, possible drivers, signal
  name changes
• Hard to correlate results with source
• Hard to grasp operation over many cycles
• Have to re-simulate to test possible fixes
• Debussy and Verdi solution
• Integrated, interactive, synchronized views
• Quickly and easily determine causality
• Click waveform to locate active driver
• Automatically trace value to its origin
• See signal values and transitions in context
• In the source code on the diagrams
• Test possible fixes while debugging
• Evaluate and propagate value changes solve for
  desired value

Demo
27
ApplicationsThroughout the Flow
Late-stage netlist changes nECO Easily locate
and isolate the logic to change Modify the design
directly in the schematic Write a new Verilog
netlist with comments Automatically creates new
wires, ports as needed Generates change scripts
to drive PR tools Generates reports to track and
manage changes
Investigate timing problems Easily locate signals
in file, scope, or design Diagrams that shows
only logic along path See SDF interconnect delays
on the diagram Calculate and display
longest/shortest paths
HDL rule checking nLint Comprehensive rule
set Batch or interactive Customizable via
User-Defined Rules Tightly integrated with other
modules for debug
Simulation dump comparison nCompare Easily
scripted into current flow Tightly integrated
with other modules for debug
28
System-Level Debug

• Challenge Expanding definition of source
  places new requirements on debug systems
• Novas Technology Solution
• Expand KDB to handle system level constructs
• Stacks, queues, etc.
• API to capture design/testbench/property data
• Work with testbench partners
• New property database
• Flexibility moving forward as languages mature

29
System-Level Debug Support

• Debug testbench source code and results in
  context of design data
• Debug property and assertion source code and
  results in context of design data
• Roadmap
• Support for Synopsys OpenVera and OpenVera
  Temporal Assertions will be first
• Working prototype in Q3
• Others will follow based on user demand

Demo
30
Active Knowledge

• Challenge Design reuse and sharing make it
  difficult to understand designs and maintain that
  understanding over time
• Novas Technology Solution
• Engines to capture and extract knowledge from
  design and verification
• Schematics, bubble diagrams
• Datapath and control flow
• Cause and effect relationships
• Topology-driven PR engine that supports
  customization
• Customize diagrams, reorganize hierarchy, bundle
  signals, add notes
• Support multiple overlapping views of the design
• Algorithms to detect HDL changes and
  automatically update captured knowledge
• Add/delete blocks while maintaining topology
• Modify connections to match description

31
Active Design Knowledge System

• Automates knowledge extraction
• Block diagrams, schematics, state machines
• Cause-and-effect relationships
• Simplifies knowledge capture
• Customize diagrams, reorganize hierarchy, bundle
  signals
• Save multiple views of same logic
• Add notes and links to external documentation
• Centralizes and preserves captured knowledge
• Intuitive library scheme
• Live update of views with HDL changes
• Maximizes knowledge sharing and reuse
• Easy browsing, querying and retrieval
• Active applications design reviews, live
  documentation, debug
• Export to other applications like FrameMaker,
  MS-Office for formal documentation

32
Knowledge Extraction,Capture, and Customization
Data Path
Full View
PLA flow
Multiple overlapping views
Topology-driven PR engine
Automatic updates track HDL changes
33
Application Examples

• Extract and capture knowledge during design
  process
• Automatically generate block diagrams,
  schematics, bubble diagrams
• Customize diagrams to capture knowledge and
  intent
• Change size, placement of blocks and text bundle
  nets
• Group and ungroup elements to add/remove
  hierarchy to picture
• Add comments, links to external documentation
• Save pictures for later use or export to
  documentation tools
• Saved pictures track source code changes
• Understand legacy code or IP for reuse in current
  design
• Review knowledge captured by original designer
• Customized diagrams
• Additional notes and details links to external
  information
• Extract knowledge from verification process for
  more detailed understanding
• Cause-and-effect, control flow
• Modify HDL and view updated information
• Blocks are added/deleted, connections are changed
• Save new knowledge for next time
• New diagrams, critical details

Demo
34
Expanding Novas Product Line
System LevelTestbench Properties
BehaviorAnalysis
Active Design Knowledge Capture Preservation Shar
ing
Temporal Visualization
nECO Gate-Level Netlist Modification
Symbolic What-If Exploration
nLint RTL Code Analysis
nCompare Simulation Result Comparison
ADVANCED DEBUG VERIFICATION
DESIGN REUSE
HDL DEBUG
35
Novas Solutions

• Debussy Knowledge-Based Debug System
• Complete, open debugging system
• Verilog, VHDL, mixed
• Simulation, formal, timing
• Cuts debug time in half
• Verdi Behavior-Based Debug System
• Revolutionary advance in debug technology
• Automates tracing, visualizes behavior over time,
  localizes evaluation of potential fixes
• Built on proven platform
• Dramatically accelerates debug and understanding
  again
• Active Design Knowledge System
• Extracts design knowledge from HDL and captures
  engineers knowledge in customized diagrams
• Automatically updates captured knowledge as HDL
  changes
• Enables shared understanding for reuse, IP, and
  debug
• Preserves investment in design understanding

36
Design Better, Debug Faster

• Economics
• Cut debug time in half
• Save tens of thousands of /engineer/year
• Return time to more productive tasks
• Ensure chips successfully meet schedule
• Technology
• Design knowledge architecture
• Open systems
• Advanced RD
• Novas
• Focus on knowledge and understanding
• Your debug partner, now and future