Enhanced JTAG to test interconnects in a SoC

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Enhanced JTAG to test interconnects in a SoC
Cours project, ELE6306, Ecole Polytechnique,
MontrealDany Lebel, Alin Herta
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Plan

• Introduction
• Interconnect Integrity definition
• Fault models adapted for the integrity
• Some JTAG 1149.1 Extensions
• New cells
• New instructions
• Review of the experimental results
• Conclusion
• References
• Questions?

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Introduction

• Motivation
• Smaller technologies
• High speed circuits in the gigahertz range
• Increasing number of cores in System on Chip
  (SoC)
• gt The interconnects become a defect hard to test
• Highly used and efficient test technique
• Boundary scan (JTAG)

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Signal integrity definition

• An interconnect defect is efficiently described
  by the signal integrity
• Signal integrity
• The expected signal is obtained
• The value at the end of the interconnection is
  exact
• Acceptable delay to obtain the expected result
• Coupling capacity and mutual inductance affect
  the integrity of a signal
• By adding Noise and extra delays
• Consequence of an integrity problem
• Shortened life of the component
• Intermittent functional problem

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Signal integrity definition

• Conclusions on the integrity
• The integrity is expressed in term of the mutual
  effects from surrounding interconnects
• Stuck at fault model useless
• A new fault model must be used
• The integrity test can be compared to analogical
  tests
• An acceptable discreet delay must be defined
• Which is not a binary value at first
• It depends of the physical configuration of each
  of the interconnects
• It therefore needs a analysis of the SoC
• Cost of a interconnect fail is very high for the
  company
• Because those problems tend to be found once the
  customer is using the product
• It is thus extremely effective to invest on the
  interconnect tests

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Fault models for integrity

• Maximum Agressor model (MA)
• The simplified model named MA shown in the figure
  uses the signal passing on a victim V which can
  be affected by the signals/transitions on
  aggressors A near to victim line.
• MA model is based just on C coupling. When mutual
  inductance appears it has been shown that MA
  doesnt reflect the worst case.
• In MA model to have a maximal ringing the victim
  line is set quiescent and all the aggressors make
  the simultaneous transition in the same
  direction.
• When is desired to have a maximal delay in MA
  model the victim line and aggressors make an
  opposite transition.

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Fault models for integrity

• Maximum Aggressor model (MA) (suite)
• One of the most important situation not covered
  by MA is when the nearest aggressors change in
  one direction and the other aggressors in the
  opposite direction.

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Fault models for integrity

• Exhaustive and pseudorandom pattern generation
• The generating of exhaustive and pseudorandom
  patterns used to cover exhausting testing shows
  that there are some cases where aggressors are in
  quiescent mode and in this situation they do not
  maximally affect the victim line for noise and
  delay.
• Thus, some cases are useless to test

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Fault models for integrity

• Maximum Transitions model (MT) (suite)
• The new fault model which covers all transitions
  on victim and multiple transitions on aggressors
  is defined as MT model.
• MT is a complete model containing all possible
  transitions, MA model being a subset of those
  transitions from MT
• MT uses double direction change of aggressors
  versus single direction change in MA model.
• Quiescent cases of aggressors lines for which
  integrity loss will not be maximal dont need to
  be taken in consideration

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Fault models for integrity

• Test on a 7 interconnect
• They contain a victim line in the middle and
  beside are the aggressors. The patterns chosen
  for MT model are
• -1) 0110110 -gt 1001001
• -2) 0110101 -gt 1001010
• and for MA model the pattern is 1110111 -gt
  0001000
• The maximum delay is created with MT patterns
  having a value between 35 and 70 ps more than MA.

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Fault models for integrity

• Number of test patterns for a group of m
  interconnects
• Npm42exp(m-1) where m is the number of
  interconnect considered
• Based on this formula the time will increase
  exponentially when we will have more
  interconnects to test so we have to find a
  solution to detect how many aggressors are
  important to be considered to decrease the time
  of test when number of interconnects will
  increase.
• We define k as a local factor who determines how
  many aggressors will have an influence on a
  victim line based on one threshold established by
  how precisely we want to consider that influence.

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Fault models for integrity

• The peak noise difference which corresponds to
  two local factors k3 and k4 is
• Vpeak(k4) Vpeak(k3)0.048V.
• This is minimal and therefore k 3 can be used
  in this case
• This value for k3 is dependent by technology and
  application.
• The choosing of local factor will be based on a
  tradeoff between longer simulation time and
  accuracy.
• In some transitions the victim line should remain
  quiescent while the aggressor lines change but in
  other transitions both the victim and aggressor
  lines will change.

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Enhanced JTAG 1149.1

• Modify JTAG for interconnection tests
• 2 New modules
• Test vector generator according to the MT fault
  model
• Integrity detection module
• 2 new instructions are added to JTAG to control
  those new modules

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Enhanced JTAG 1149.1 test generator

• Modify BSC to get a PGBSC (Pattern Generation
  BSC)
• Allows to avoid all the vectors to be sent
  through input the scan chain
• Made with a seed that generates multiple test
  vectors
• Number of seed to send depends on the number of
  interconnects k
• Hardware added
• Only for the BSC cells that we want to use as
  integrity test generator

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Enhanced JTAG 1149.1 test generator

• Example with m 3 interconnects

• The middle line is the victim, while the other
  two are aggressors
• The initial table is rearrange as to obtain this
  new table
• For one seed, we test all the victims
• One shift of the scan chain (A-V pattern) because
  we keep looping to the original seed
• (m)2exp(m-1) 12 seeds are necessary
• We have to use each seed 3 times
• We need to send the new seed through the TDI
  input and restart the test for all the victims
  again

• Rappel
• 2 interconnections voisines
• dune victime sont
• considérés aggresseurs

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Enhanced JTAG 1149.1 test generator

• We can see a cyclic pattern for the victim and
  aggressors
• The value assigned to the victim changes every
  two clocks
• The value assigned to the aggressors change every
  clock
• We therefore need to generate a second clock
  which is 2 times slower than the original one

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Enhanced JTAG 1149.1 test generator

• PGBSC cell
• Only one extra control signal
• The aggressor/ victim pattern is sent to FF1 with
  some shifts from the TDI input
• Q1 (the aggressor/ victim pattern ) is shifted
  when 1 seed is completed for the current victim

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Enhanced JTAG 1149.1 Integrity observation cell

• Modify BSC to get a OBSC (Observation BSC)
• Allows to detect integrity problems
• The cell has a memory element that keeps the
  information if there was a violation or not
  during the previous cycles.
• Can be sampled as needed according to the speed
  and level of the detail of the fail needed
• Capture and send the result to TDO (captureDR and
  shiftDRs states)
• Once after all the tests were done for all the
  victims
• gt Not expensive but less informative on the
  location of the fail
• After each seed for each victim
• gt Compromise on the cost/information on the fail
• After each test vector
• gt Very expensive but very informative

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Enhanced JTAG 1149.1 Integrity observation cell

• Choice depends on
• The level of confidence in the process
• The will to identify where is the fault for debug
  purposes VS simply put aside the component that
  fails
• Time of test suitable before to be informed of
  the failing result
• Hardware added
• Only for the BSC cells that we want to observe
  the integrity
• Possibility to merge the two cells created in an
  universal one
• Area cost associated

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Enhanced JTAG 1149.1 Integrity observation cell

• OBSC cell
• Only 2 extra control signals (SI and CE)
• It allows to capture the result of the ILS in FF1
  flip-flop
• The result is sent to the next OBSC cell while
  shifting (shiftDR)

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Enhanced JTAG 1149.1 Integrity observation cell

• Propagation of the integrity result to the test
  output TDO

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Enhanced JTAG 1149.1 Integrity observation cell

• Détails of the ILS cell (Integrity Loss Sensor)

Table de vérité XNOR
A X C
0 0 1
0 1 0
1 0 0
1 1 1
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Enhanced JTAG 1149.1 Integrity observation cell

• Timing diagrams for the detection of an integrity
  fault
• Acceptable Delay Region (ADR)
• ADR t(XNOR) t(INV1) t(NAND) t(INV2)

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Enhanced JTAG 1149.1 Integrity observation cell

• Tuning the ILS cell
• Sizing of the INV1 and INV2 invertors allows to
  adjust ADR (Acceptable Delay Region)
• The delay from INV2 is kept tunable to take into
  account the topology of the interconnect and the
  process variations

T(INV1) 10 t(NOT) T(INV2) t(NOT) ADR ps
5 1 450
3 3 250
1 5 100
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Enhanced JTAG 1149.1 system

• Architecture used in test

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Enhanced JTAG 1149.1 new instructions

• For signal integrity test, there are two new
  instructions
• G-SITEST to activate the new cell PGBSCs to
  generate patterns for test
• O-SITEST to read out the integrity test result .
• 1) G-SITEST Instruction
• When is used the new enhanced boundary scan
  architecture G-SITEST will generate test pattern.
  
• The core before core i executes the BYPASS
  instruction to scan seeds from the system input.
• The core i executes the PRELOAD instruction for
  the seed.

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Enhanced JTAG 1149.1 new instructions

• After will follow G-SITEST instruction which
  takes place in Update-IR controller state with
  all the signals related activated.
• The signal SI1 will activate PGBSC cell in
  integrity mode and the signal CE1 will enable
  the ILS cells to capture signal integrity
  information.
• During the Shift-DR state the victim-select data
  is shifted into FF1 of PGBSCs.
• Every Update-DR will generate anew pattern for MT
  model.

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Enhanced JTAG 1149.1 new instructions

• 2) O-SITEST Instruction
• One instruction O-SITEST is loaded after the
  execution of one instruction
• when the loss information has been stored in ILS
  FF of OBSC cell.
• The role of O-SITEST is to capture and scan out
  the content of ILS FF.
• The instruction is decoded in the Update-IR state
  and after the control signals SI 1 and CE 0
  (to deactivate ILS) are generated .
• All the cores after j will execute BYPASS
  instruction to scan out data to system output.

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Enhanced JTAG 1149.1 new instructions

• G-SITEST using PGBSC will generate patterns for
  test
• Simultaneously OBSC captures information at the
  receiving end of interconnects
• The integrity information reading after
  application of test is done with O-SITEST
  instruction
• Here is the algorithm written with the new
  instructions

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Simulation Results

• The table shows that the enhanced cells as PGBSC
  and OBSC are 28-46 more expensive compared with
  conventional BSC but this is not so expensive
  compared to the overall cost of boundary scan
  architecture.
• The user has the possibility of
  inserting/changing cells on only the
  interconnects of interest so the price in this
  case could go lower.

Table VI, COST ANALYSIS FOR BSCs Table VI, COST ANALYSIS FOR BSCs Table VI, COST ANALYSIS FOR BSCs Table VI, COST ANALYSIS FOR BSCs
Test Architecture Cost NAND Cost NAND Cost NAND
Test Architecture Sending Observing Bidirectional
Conventional Cells 26 26 78
Enhanced Cells 36 38 100
Area Increase 38.5 46.2 28.2
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Simulation Results

• The Table shows the difference between the
  application of MT model in test using enhanced
  boundary scan and conventional boundary scan.
• The more interconnects (n) we have, the faster
  the test is run with our JTAG extension compared
  to the original JTAG

Table VII, MT PATTERN APPLICATION TIME Cycle (p0) Table VII, MT PATTERN APPLICATION TIME Cycle (p0) Table VII, MT PATTERN APPLICATION TIME Cycle (p0) Table VII, MT PATTERN APPLICATION TIME Cycle (p0) Table VII, MT PATTERN APPLICATION TIME Cycle (p0) Table VII, MT PATTERN APPLICATION TIME Cycle (p0) Table VII, MT PATTERN APPLICATION TIME Cycle (p0)
Methods MT-Pattern Application Time Cycle (p0) MT-Pattern Application Time Cycle (p0) MT-Pattern Application Time Cycle (p0) MT-Pattern Application Time Cycle (p0) MT-Pattern Application Time Cycle (p0) MT-Pattern Application Time Cycle (p0)
Methods n8 n8 n16 n16 n32 n32
Methods k2 k3 k2 k3 k2 k3
Nclk_EBS 2560 17920 3840 25088 6400 39424
Nclk_BS 19200 150528 32000 250880 57600 451584
Time Reduction 86.1 88.5 88.3 90.3 88.9 91.8
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Simulation Results

• The following table compares three methods
• Method 1 which has the least test time and a
  disadvantage for not being able to determine
  which transition have caused the fault in an
  interconnect.
• Method 2 provides more information to determine
  which set of transitions or faults caused the
  violation in the interconnects at the expense of
  more test time.
• Method 3 is the most informative one but its
  extremely time consuming.
• In the end method 2 can be used to tradeoff test
  time versus accuracy.

Table VIII, OBSERVATION-TEST TIME FOR THREE METHODS Table VIII, OBSERVATION-TEST TIME FOR THREE METHODS Table VIII, OBSERVATION-TEST TIME FOR THREE METHODS Table VIII, OBSERVATION-TEST TIME FOR THREE METHODS Table VIII, OBSERVATION-TEST TIME FOR THREE METHODS Table VIII, OBSERVATION-TEST TIME FOR THREE METHODS Table VIII, OBSERVATION-TEST TIME FOR THREE METHODS
Methods Observation Test Time Cycle (q0) Observation Test Time Cycle (q0) Observation Test Time Cycle (q0) Observation Test Time Cycle (q0) Observation Test Time Cycle (q0) Observation Test Time Cycle (q0)
Methods n8 n8 n16 n16 n32 n32
Methods k2 k3 k2 k3 k2 k3
Method 1 8 8 16 16 32 32
Method 2 640 3584 1280 7168 2560 14336
Method 3 2560 14336 5120 28672 10240 57344
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Simulation Results

• Table IX shows the differences between MA and MT
  models from noise voltage and skew point of view
  for different local factor k.
• If local factor is k3, 4 there is a higher
  difference in delay between MA and MT model
  compared with the difference in peak noise.
• MT is better to test the worst integrity case

Table IX, MT and MA Comparison Table IX, MT and MA Comparison Table IX, MT and MA Comparison Table IX, MT and MA Comparison Table IX, MT and MA Comparison
k Observation Test Time Cycle (q0) Observation Test Time Cycle (q0) Observation Test Time Cycle (q0) Observation Test Time Cycle (q0)
k MT MT MA MA
k Vnoise V Delay ps Vnoise V Delay ps
k2 0.351 470.5 0.384 468.5
k3 0.408 472.3 0.404 450.7
k4 0.420 483.4 0.411 440.9
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Conclusion

• The proposed MT fault model is a superset of MA
  model and is much more capable of testing the
  capacitive and inductive couplings among
  interconnects based on JTAG boundary-scan
  architecture.
• The modifications to do to the current JTAG
  1149.1 are
• Modified generation cell
• Modified scan cells
• Modifications to the TAP controller to handle two
  new instructions.
• The advantage of this proposed architecture is
  that it provides cost-effective solution for
  through testing of interconnects using the
  popular JTAG standard.
• The performance results show a net improvement
  which can easily be translated to a cost
  effective solution for a SoC.

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References

• 1 Joint Test Action Group (JTAG) 1149.1
  documentation Available http//www.jtag.com/
  online
• 2 Mohammad H Tehranipour, Nisar Ahmed and
  Mehrdad Nourani, Test SoC Interconnects for
  signal Integrity using extended JTAG, IEEE,
  2004.
• 3 S. Naffziger, Design methodologies for
  interconnects in GHz ICs, presented at the Int.
  Solid Stat Conf., 1999
• 4 Synopsys design compiler description
  Available http//www.synopsys.com/products/logic/
  design_compiler.html online
• 5 N. Ahmed, M. H. Tehranipour and M. Nourani,
  Extending JTAG for testing signal integrity in
  SoCs, 2003
• See all the references of article mentioned above.

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Questions?