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Sequential CMOS and NMOS Logic Circuits

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Title: Sequential CMOS and NMOS Logic Circuits


1
Sequential CMOS and NMOS Logic Circuits
  • Sequential logic circuits contain one or more
    combinational logic blocks along with memory in a
    feedback loop with the logic
  • The next state of the machine depends on the
    present state and the inputs
  • The output depends on the present state of the
    machine and perhaps also on the inputs
  • Mealy machine output depends only on the state
    of the machine
  • Moore machine the output depends on both the
    present state and the inputs
  • Topics to be studied in this section
  • Basic memory cell operation
  • SR Latch
  • JK Latch
  • D Latch
  • Flip-Flops
  • Clocked CMOS Logic
  • Cascode Voltage Switch Logic
  • Clock Distribution

From Chapter 8 in Kang and Leblebici,
and portions of Chapter 5 in West and Eshraghian
R. W. Knepper SC571, page 5-27
2
Logic Circuit Classification Sequential Circuit
Types
  • Sequential circuits (also called regenerative
    circuits) fall into three types
  • Bistable
  • Monostable
  • Astable
  • Bistable circuits have two stable operating
    points and will remain in either state unless
    perturbed to the opposite state
  • Memory cells, latches, flip-flops, and registers
  • Monostable circuits have only one stable
    operating point, and even if they are temporarily
    perturbed to the opposite state, they will return
    in time to their stable operating point
  • Astable circuits have no stable operating point
    and oscillate between several states
  • Ring oscillator

R. W. Knepper SC571, page 5-28
3
Memory Cell Two-Inverter Basic Bistable Element
  • A memory cell is comprised of two inverters
    connected back-to-back, i.e. output of one to
    input of the other and vice-versa.
  • The memory cell (or latch) has two stable states
    where the dc voltage transfer curves cross at the
    VOH and VOL points, but also exhibits an unstable
    state where the VTCs cross near their Vth
    switching points.
  • In actual physical circuits the memory cell will
    never stay at the unstable point, since any small
    electrical noise in the circuit will trigger it
    to one side or the other
  • In numerical simulation (Cadence Spectre) the
    circuit may actually remain in the unstable state
    (assuming no noise source)
  • The CMOS SRAM cell at the left will either be in
    state 0 with V01 at GND and V02 at VDD or in
    state 1 with V01 at VDD and V02 at GND.

R. W. Knepper SC571, page 5-29
4
CMOS SR Latch NOR Gate Version
  • The NOR-based SR Latch contains the basic memory
    cell (back-to-back inverters) built into two NOR
    gates to allow setting the state of the latch.
  • If Set goes high, M1 is turned on forcing Q low
    which, in turn, pulls Q high
  • S1 ? Q 1
  • If Reset goes high, M4 is turned on, Q is pulled
    low, and Q is then pulled high
  • R1 ? Q 1
  • If both Set and Reset are low, both M1 and M4 are
    off, and the latch holds its existing state
    indefinitely
  • If both Set and Reset go high, both Q and Q are
    pulled low, giving an indefinite state.
    Therefore, RS1 is not allowed
  • The gate-level symbol and truth table for the
    NOR-based SR latch are given at left
  • To estimate Set time, add time to discharge Q
    time to charge Q (pessimistic result)

R. W. Knepper SC571, page 5-30
5
Depletion Load NMOS SR Latch NOR Version
  • A depletion load version of the NOR-based SR
    latch is shown at left.
  • Functionally same as CMOS version
  • The latch is a ratio circuit
  • Low side conducts dc current, causing higher
    standby power than CMOS version

R. W. Knepper SC571, page 5-31
6
CMOS SR Latch NAND Gate Version
  • A CMOS SR latch built with two 2-input NAND gates
    is shown at left
  • The basic memory cell comprised of two
    back-to-back CMOS inverters is seen
  • The circuit responds to active low S and R inputs
  • If S goes to 0 (while R 1), Q goes high,
    pulling Q low and the latch enters Set state
  • S0 ? Q 1 (if R 1)
  • If R goes to 0 (while S 1), Q goes high,
    pulling Q low and the latch is Reset
  • R0 ? Q 1 (if S 1)
  • Hold state requires both S and R to be high
  • S R 0 if not allowed, as it would result in
    an indeterminate state

R. W. Knepper SC571, page 5-32
7
Clocked SR Latch NOR Version
  • Shown at left is the NOR-based SR latch with a
    clock added.
  • The latch is responsive to inputs S and R only
    when CLK is high
  • When CLK is low, the latch retains its current
    state
  • Timing diagram shows the level-sensitive nature
    of the clocked SR latch.
  • Note four times where Q changes state
  • When S goes high during positive CLK
  • On leading CLK edge after changes in S R during
    CLK low time
  • A positive glitch in S while CLK is high
  • When R goes high during positive CLK

R. W. Knepper SC571, page 5-33
8
Clocked CMOS SR Latch AOI Implementation
  • CMOS AOI implementation of clocked NOR-based SR
    latch shown at left with logic symbol circuit
    below
  • Only 12 transistors required
  • When CLK is low, two series legs in N tree are
    open and two parallel transistors in P tree are
    ON, thus retaining state in the memory cell
  • When CLK is high, the circuit becomes simply a
    NOR-based CMOS latch which will respond to inputs
    S and R

R. W. Knepper SC571, page 5-34
9
Clocked CMOS JK Latch NAND Version
  • The SR latch has a problem in that when both S
    and R are high, its state becomes indeterminate
  • The JK latch shown at left eliminates this
    problem by using feedback from output to input,
    such all states in the truth table are allowable
  • If J K 0, the latch will hold its present
    state
  • If J 1 and K 0, the latch will set on the
    next positive-going clock edge, i.e. Q 1, Q
    0
  • If J 0 and K 1, the latch will reset on the
    next positive-going clock edge, i.e. Q 1 and Q
    0
  • If J K 1, the latch will toggle on the next
    positive-going clock edge
  • Note that in order to prevent the JK Latch above
    from oscillating continuously during the clock
    active time, the clock width must be kept smaller
    than the switching delay time of the latch.
    Otherwise, several oscillations may occur before
    the clock goes low again. In practice this may
    be difficult to achieve.

R. W. Knepper SC571, page 5-35
10
JK Master-Slave Flip-Flop
  • A Flip-Flop is defined as two latches connected
    serially and activated with opposite phase clocks
  • First latch is the Master Second latch is the
    Slave
  • Eliminates transparency, i.e. a change occurring
    in the primary inputs is never reflected directly
    to the outputs, since opposite phase clocks are
    used to activate the M and S latches.
  • A JK master-slave flip-flop (NOR-based version)
    is shown below
  • The feedback paths occur from Q and Q slave
    outputs to the master inputs AOI gates
  • does not exhibit any tendency to oscillate when J
    K 1 no matter how long the clock period,
    since opposite clock phases activate the master
    and slave latches separately.
  • The NOR-based version can be done with four AOI
    CMOS gates, requiring 28 transistors
  • Can be susceptible to ones catching, i.e. a
    positive glitch in either the J or K input while
    the CLK is high, which can change the state of
    the master latch (and the slave latch on next
    edge)

R. W. Knepper SC571, page 5-36
11
CMOS D-Latch Implementation
  • A D-latch is implemented, at the gate level, by
    simply utilizing a NOR-based S-R latch,
    connecting D to input S, and connecting D to
    input R with an inverter.
  • When CLK goes high, D is transmitted to output Q
    (and D to Q)
  • When CLK goes low, the latch retains its previous
    state
  • The D latch is normally implemented with
    transmission gate (TG) switches, as shown at the
    left
  • The input TG is activated with CLK while the
    latch feedback loop TG is activated with CLK
  • Input D is accepted when CLK is high
  • When CLK goes low, the input is open-circuited
    and the latch is set with the prior data D

R. W. Knepper SC571, page 5-37
12
CMOS D-Latch Schematic View and Timing
  • A schematic view of the D-Latch can be obtained
    using simple switches in place of the TGs
  • When CLK 1, the input switch is closed allowing
    new input data into the latch
  • When CLK 0, the input switch is opened and the
    feedback loop switch is closed, setting the latch
  • Timing diagram
  • In order to guarantee adequate time to get
    correct data at the first inverter input before
    the input switch opens, the data must be valid
    for a given time (Tsetup) prior to the CLK going
    low.
  • In order to guarantee adequate time to set the
    latch with correct data, the data must remain
    valid for a time (Thold) after the CLK goes low.
  • Violations of Tsetup and Thold can cause
    metastability problems and chaotic transient
    behavior.

R. W. Knepper SC571, page 5-38
13
Alternate CMOS D-Latch Implementation
  • An alternate (preferred) version of the CMOS
    D-Latch (shown at left) is implemented with two
    tri-state inverters and a normal CMOS inverter.
  • Functionally it is similar to the previous chart
    D-Latch
  • When CLK is high, the first tri-state inverter
    sends the inverted input through to the second
    inverter, while the second tri-state is in its
    high Z state.
  • Output Q is following input D
  • When CLK is low, the first tri-state goes into
    its high Z state, while the second tri-state
    inverter closes the feedback loop, holding the
    data Q and Q in the latch.

R. W. Knepper SC571, page 5-39
14
CMOS Static Latches with Single Phase Clock
  • Various types of D latch circuit with single
    phase clocks
  • (a) shows the use of a weak inverter with long L
    (low W/L) devices to allow removal of feedback
    loop X-gate but retain static latch function
  • (b) D latch ckt with input inverter buffer
  • (c) implementation of (b) utilizing tri-state
    buffer/inverter circuits with clocks at center of
    tri-state
  • Alternate schematic of (c) indicating layout
    convenience due to common tie point at output of
    tri-state buffers
  • Clock skew problems can be solved on-chip by
    using buffering in clock nets
  • Inverter buffers to generate neg clk
  • Transmission gate buffers for true clk

R. W. Knepper SC571, page 5-40
15
Construction of D Register (Flip-Flop) in CMOS
  • Two level-sensitive latches are combined to form
    a positive edge-triggered register, as is used to
    build a D register
  • (a) shows negative level sensitive latch (valid
    when clock is negative)
  • (b) shows positive level sensitive latch (valid
    when clock is positive)
  • (c) shows positive edge-triggered D register
    (also called a Flip-Flop) comprised of a negative
    latch feeding a positive latch
  • First latch is the Master
  • Second latch is the Slave
  • D register timing
  • Output Q valid at Tq (clock-to-Q) delay after
    clock edge
  • Data must be valid Ts (setup time) prior to clock
    edge and Th (hold time) after clock edge

R. W. Knepper SC571, page 5-41
16
CMOS D Flip-Flop Falling Edge-Triggered
  • Shown below is a D Flip-Flop, constructed by
    cascading two D-Latch circuits from the previous
    chart
  • Master latch is positive level sensitive
    (receives data when CLK is high)
  • Slave latch is negative level sensitive (receives
    data Qm when CLK is low)
  • The circuit is negative-edge triggered
  • The master latch receives input D until the CLK
    falls from high to low, at which point it sets
    that data in the master latch and sends it
    through to the output Qs

R. W. Knepper SC571, page 5-42
17
Clocked CMOS Logic (C2MOS)
  • Clocked CMOS logic has been used for very low
    power CMOS and/or for minimizing hot electron
    effect problems in N-FET devices
  • Clocking transistors allow valid logic output
    only when clk is high
  • Clocking transistors may be at output end of
    logic trees (maximum performance) or at power
    supply end of logic trees (maximum protection
    from hot electrons)

R. W. Knepper SC571, page 5-43
18
Cascade Voltage Switch Logic (CVSL)
  • CVSL is a differential type of logic circuit
    whereby both true and complement inputs are
    required
  • For example, true inputs are applied to left
    pull-down leg below and complement inputs are
    applied to right leg
  • N pull-down trees are the dual of each other
  • P pull-up devices are cross-coupled to latch
    output
  • Both true and complement outputs are obtained
  • Input pull-down trees may be intermixed,
    depending on the logic to be implemented

R. W. Knepper SC571, page 5-44
19
Clocked CVSL (Cascade Voltage Switch Logic)
  • Clocked CVSL circuit type shown at left
  • Example in (b) is an implementation of Q a XOR
    b XOR c XOR d
  • Some similarity to a current steering circuit in
    bipolar
  • When clock is low, nodes are precharged When
    clock goes high, one leg pulls the internal
    output to ground, while opposite leg is
    non-conducting
  • Complement outputs Q and Q are obtained

R. W. Knepper SC571, page 5-45
20
Sample-Set Differential Logic (SSDL) Dynamic
CVSL with a Latching Sense Amp
  • SSDL utilizes a latching sense amplifier to latch
    output when clock goes high, much like a DRAM
    sense amplifier
  • When clock is low P1 P2 precharge while N1
    pulls down the N tree logic causing a
    differential voltage on the internal output nodes
  • When clock goes high, N3-N5 cause the sense
    amplifier to set and latch

R. W. Knepper SC571, page 5-46
21
CMOS Schmitt Trigger Circuit
  • The Schmitt Trigger circuit, shown at left, has a
    dc transfer characteristic like an inverter, but
    with different switching thresholds depending on
    whether Vin is increasing or decreasing
  • Hysteresis effect
  • If Vin is increasing, high Vth
  • If Vin is decreasing, low Vth
  • SPICE simulated VTC waveforms with increasing and
    decreasing input voltage are shown at right.
  • increasing Vin ? Vth 3.5 V
  • decreasing Vin ? Vth 1.4 V

R. W. Knepper SC571, page 5-47
22
Clocking Strategies for Finite State Machine
Pipelined Systems
  • VLSI systems universally make use of storage
    elements and states, with clock(s) to control the
    sequencing
  • (a) shows a Finite State Machine
  • at positive clock edge, the next state bits get
    stored as the current state bits and the current
    state bits combined with inputs generate new next
    state bits
  • (b) shows a pipelined system indicative of
    todays microprocessors and logic systems

R. W. Knepper SC571, page 5-48
23
Timing a Pipelined System
  • Pipelined system typically has registers
    separated by combinational logic
  • Minimum cycle time Tc obtainable given by
  • Tc Tq Td Ts
  • Tq is the clock-to-Q output delay of Register A
  • Td is the total worst case delay through the
    combinational logic
  • Ts is the set-up delay time of Register B
  • In order to increase frequency in superpipelined
    and superscalar machines, long combinational
    logic blocks can be split into smaller
    combinational blocks and latches used to separate
    the blocks (rather than full registers)
  • Improves overall frequency of processor, but adds
    some delay penalty due to added latches

R. W. Knepper SC571, page 5-49
24
The Effect of Clock Skew on a Pipeline
  • Design of a pipelined machine assumes that clock
    edges will appear at each register at a precise
    time to
  • If delay occurs in clock distribution due to RC
    wire delays, LC ringing on the clock nets, or
    buffer delay, the pipeline timing will be skewed.
  • Can cause a latch or register to be set with
    incorrect data (as shown at right)
  • Example
  • Register M1 is set by the clock at Tc1, providing
    data inputs to the combinational logic and then
    to register M2
  • Register M2 is supposed to latch in old data at
    the same clock edge
  • But, if the delay to Tc2 gt Tc1 Tq1 logic
    delay, M2 will incorrectly store the new data
    rather than the previous data.

R. W. Knepper SC571, page 5-50
25
Clock Synchronization Using Phase Locked Loops
  • Phase Locked Loop (PLL) is used to synchronize an
    on-chip generated clock with a system clock at
    some point on the chip
  • Reduces clock skew to zero at the sensing point
  • (a) no PLL clock skew
  • (b) with PLL on chip
  • (c) using PLL with divide by 4 scheme to achieve
    4X freq on-chip
  • (d) use of PLL approach to synchronize data
    across several chips

R. W. Knepper SC571, page 5-51
26
Charge Pump Phase Locked Loop
  • One implementation of a PLL using a phase
    detector and charge pump ckt with a freq
    multiplier of n times
  • A phase difference is measured between the
    reference clock and the on-chip clock
  • Charge pump pumps a ref voltage up or down
    depending on phase difference
  • Loop filter to clean up voltage
  • Variable Controller Oscillator (VCO) is used to
    obtain exact frequency clock
  • (b) VCO frequency is a function of control
    voltage applied to N pull-downs and current
    mirror
  • (c) another approach to control frequency by
    using a variable delay line
  • MOS capacitance load on each stage is varied by
    NFET gate voltage

R. W. Knepper SC571, page 5-52
27
Latch Metastability
  • Consider the problem of setting a latch when the
    data is late and/or has a very long rise/fall
    time and is still changing during the clock
    transition
  • if data change is delayed and overlaps clock edge
    (below), latch may set with new data rather than
    valid prior data
  • Data delay 2.2 ns ? latch sets correctly at
    Q1
  • Data delay 2.3 ns ? latch hangs momentarily at
    metastable point, but then sets correctly at Q1
  • Data delay 2.4 ns ? latch hangs momentarily
    and sets incorrectly at Q0
  • Metastable point non stable point in a latch
    where Vleft Vright (neither 0 or 1)
  • thermal noise will cause latch to move off
    metastable point and set at a 0 or a 1
  • How to fix?
  • speedup the data (register-based synchronizer)
  • delay the clock (introduce an intentional clock
    delay ---- risky!!)

R. W. Knepper SC571, page 5-53
28
Clock Tree Distribution
  • To prevent clock skew problems on a chip, clock
    distribution networks are designed very carefully
  • Example shown linear (E-W) clock tree
    distribution network
  • Clock is buffered several times before driving
    FO3
  • Each FO3 buffer drives another high FO (FO4
    shown) buffer
  • Finally another single buffer is used for each
    linear clock line to drive across chip or
    functional island on a chip
  • H tree distribution network often used on chips
    with area pads (solder bumps)
  • Master clock is brought on board chip near
    central part of chip and driven outward with
    large H interconnection arrangement

R. W. Knepper SC571, page 5-54
29
JK MS Flip-Flop Problem Ones Catching
  • Although the JK Master-Slave Flip-Flop can be
    considered edge-triggered in regards to a change
    in Qs at the negative CLK edge, it is actually
    level sensitive in regards to noise on J (or K)
    during the CLK high interval.
  • Note positive glitch in J which erroneously Sets
    the Master latch at Qm 1 during the CLK high
    interval and then also reflects itself in Qs 1
    at the negative-going CLK edge.
  • Called Ones Catching
  • Same problem can occur with a glitch in K during
    CLK high, causing a Reset operation
  • Since the master latch actually sets and latches
    on the noise glitch, the error is then
    transmitted to the slave latch during CLK

R. W. Knepper SC571, page 5-36a
30
A Positive-Edge Triggered D Flip-Flop
  • Why is the NAND-based D Flip-Flop shown at left
    edge-triggered and not level sensitive?
  • There is no master latch
  • The two NAND gate pairs are clocked with opposite
    phase clocks, and therefore act similar to the
    transmission gates in the TG-based D flip-flop
  • The 1st NAND pair is clocked with CLK
  • The 2nd NAND pair is clocked with CLK CLK
  • Result
  • Q changes on the positive-going CLK edge
  • NAND 1 pair locks in the valid data at the
    negative CLK edge
  • The master latch is essentially dynamic, holding
    the state as charge at the inputs of the two
    inverters

R. W. Knepper SC571, page 5-36b
31
Monostable Multivibrator Circuit with Depletion
Loads
  • The monostable multivibrator circuit at left has
    only one stable state (Vout low)
  • Operation (Reset)
  • Pull Vin high momentarily to reset to Vout high,
    pulling left node down to some VOL
  • Capacitor immediately pulls gate of right NMOS
    down turing it OFF
  • Vout immediately charges high to Vdd
  • Operation (Timed return to Set)
  • Capacitor slowly charges to roughly Vdd through
    NMOS depletion transistor
  • After capacitor charges sufficiently towards Vdd,
    right-most NMOS transistor turns ON and switches
    the latch back to Vout low

R. W. Knepper SC571, page 5-47b
32
An NMOS Schmitt Trigger Circuit
  • Transistor Sizes
  • W/L)M1 1
  • W/L)M2 0.5
  • W/L)M3 10
  • W/L)M4 1
  • How does the circuit work?

R. W. Knepper SC571, page 5-47a
33
Clocked SR Latch NAND Version
  • NAND version of clocked SR latch with active high
    clock is shown
  • Circuit is implemented with four NAND gates, not
    with an AOI or OAI
  • 16 transistors required
  • The latch is responsive to S or R only if CLK is
    high
  • When CLK is low, the latch retains its present
    state

R. W. Knepper SC571, page 5-31c
34
JK Register Implemented in CMOS
  • JK register is implemented by adding logic to
    front of a D register
  • Operation
  • If JK 01, Q goes to 0 on rising clock edge
  • If JK 10, Q goes to 1 on clock edge
  • If JK 00, Q retains prior state
  • If JK 11, Q toggles on clock edge
  • When clock is down, Q and QN hold prior state

R. W. Knepper SC571, page 5-47
35
T Register CMOS Implementation
  • T (Toggle) Register is shown below (note error in
    Weste Eshraghian text)
  • Output Q toggles (changes state) on each positive
    clock edge
  • Used as a divide by two counter
  • Comprised of D register with Q connected to the
    input
  • Clear function is added to the T reg below by
    replacing 1st inverter in slave latch with a NAND
  • Operation
  • When clk goes up, output Q is complemented (and
    master latch is set)
  • When clk goes down, slave latch is set. No
    change occurs to Q
  • When clear goes high, QM is set to a 1 (Q to a
    0)

R. W. Knepper SC571, page 5-46
36
D Register Implementation in CMOS
  • CMOS implementation of the popular positive
    edge-triggered D register is shown
  • Comprised of four transmission gates and five
    inverters
  • Operation
  • Clock 0
  • Master latch is connected to input to receive new
    D data
  • Slave latch is holding previous data on output
    and is isolated from input
  • Clock 1
  • Master latch stops sampling input, latches up the
    D data at the positive clock edge, and sends it
    through to the output Q

R. W. Knepper SC571, page 5-45
37
CMOS Latch Symbolic Layouts
  • Typical layouts of D latch circuits
  • (a) layout of tri-state buffer D latch shown on
    previous slide
  • (b) (c ) two alternate layouts of conventional
    D-latch circuit

R. W. Knepper SC571, page 5-51
38
Static Registers Based on CVSL and SRAM Structures
  • (a) shows a static D register designed around
    CVSL circuits
  • Latch 1 is formed with PFETs cross coupled and
    is clocked with NFETs pulling down to cause
    latch to set
  • Latch 2 is formed with NFETs cross coupled and
    uses PFET transistors to pull the output nodes
    toward Vdd to set the latch when Clk is low
  • (b) is a D latch based on an SRAM cell with NFET
    pull-downs to set latch when Clk goes high

R. W. Knepper SC571, page 5-51a
39
Differential Split-Level CVSL
  • Vref is applied to gates of cascode NFETs to
    isolate the logic signal inputs from the high
    speed output nodes
  • Vref is designed to be approximately equal to
    (Vdd/2) Vtn
  • By using Vref, the signal swing on the N logic
    trees connected to nodes d and d is reduced to a
    small voltage of roughly Vdd/2
  • P pull-up devices are wired as a cross-coupled
    latch designed with a full Vdd signal
  • Gates of P pull-up transistors are connected
    below the N cascode transistors for maximum speed
  • (a) shows a simple inverter
  • (b) shows open drain pull-down complementary
    outputs
  • N logic trees connect to d and -d

R. W. Knepper SC571, page 5-36
40
Registers with Asynchronous Set and Reset
  • Asynchronous Set and Reset are added to the D
    Register by replacing inverter gates with 2-input
    NAND gates in forward or feedback latch legs (as
    shown at left)
  • (a) Asynchronous Reset only
  • (b) Asynchronous Set and Reset
  • Both registers have an input buffer added

R. W. Knepper SC571, page 5-52
41
Dynamic Latches with a Single Clock
  • Dynamic latches eliminate dc feedback leg by
    storing data on gate capacitance of inverter (or
    logic gate) and switching charge in or out with a
    transmission gate
  • Minimum frequency of operation is typically of
    the order of 50-100 KHz so as not to lose data
    due to junction or gate leakage from the node
  • Can be clocked at high frequency since very
    little delay in latch elements
  • Examples
  • (a) or (b) show simple transmission gate latch
    concept
  • (c ) tri-state inverter dynamic latch holds
    data on gate when clk is high
  • (d) and (e) dynamic D register

R. W. Knepper SC571, page 5-53
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