VHDL Slicer Design and Implementation of a Slicer for VHDL Programs.

1
VHDL SlicerDesign and Implementation of a Slicer
for VHDL Programs.

• Program Slicing Analysis technique of
  extracting parts of a given program, relevant to
  the aspects being analyzed (the slicing
  criterion).
• E.g. slicing criterion ltline number, variablegt
  
  slice subset of the statements in the
  program that affect the variable at that
  line number.
• Applications
• Debugging
• Component Extraction
• Maintenance
• State Space Reduction in Formal Verification

2

• read(n)
• i1
• sum 0
• product 1
• while iltn do
• sum sum i
• productproduct i
• i i 1
  
• write(sum)
• write(product)
• Slicing criterion ltline number, variablegt

• read(n)
• i1
• product 1
• while iltn do
• productproduct i
• i i 1
  
• write(product)
• slice wrt lt10,productgt

3

• Slicing Criterion for VHDL Programs An output
  signal (s).
• Requirements For any input vector the behaviour
  of the slice, w.r.t. signal s should be identical
  to that of the original program.

4
VHDL Program
CFG
AST
DDS
CDS
PDG
Entity1.PDG
Sliced VHDL Program
Entity2.PDG
Reduced SDG
SDG
Slicing criterion
EntityN.PDG
VAUL VHDL Analyzer and Utility Library AST
Abstract Syntax Tree PDG Program Dependence
Graph CFG Control Flow Graph SDG System
Dependence Graph DDS Data Dependence
SubGraph CDS Control Dependence SubGraph
5

• Entity adder is Architecture rtl of adder
  is
• port(a,b,cin in bit slt a xor b
• sum,cout out bit) sumlt s xor cin
• End adder cout lt (a and b) or (s and cin)
• end rtl
• Program Dependence Graph