ASC, a SystemC extension for modeling Asynchronous Systems, and its application to an Asynchronous N

1
ASC, a SystemC extension for modeling
Asynchronous Systems, and its application to an
Asynchronous NoC

• Cédric Koch-Hofer(1), Marc Renaudin(1), Yvain
  Thonnart(2), Pascal Vivet(2)
• (1) TIMA laboratory (CNRS-INPG-UJF), 46 Av. Félix
  Viallet, 38031 Grenoble FRANCE
• (2) MINATEC, CEA-LETI, 17 rue des Martyrs, 38054
  Grenoble FRANCE
• cedric.koch-hofer, marc.renaudin_at_imag.fr
• yvain.thonnart, pascal.vivet_at_cea.fr

2
Outline

• Asynchronous NoC and SystemC
• Asynchronous SystemC (ASC)
• Asynchronous NoC modeling
• Conclusion

3
Context and Motivations

• Network On Chip
• High throughput, low power,scalability,
  modularity, QoS.
• Asynchronous and GALS architecture
• Low power, eases DFS,removes chip level timing
  constraints.
• Platform Modeling
• Offer to users high level modeling of new NoC
  protocols,
• Open framework / multi-abstraction level is
  required.
• gt Use SystemC for Asynchronous NoC modeling

FAUST ANOC chip (130 nm)
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Asynchronous Circuits modeling

• Asynchronous circuits modeling languages
• Modeled usually at handshake level,
• Dedicated languages
• CHP, Haste (ex. Tangram), Balsa,
• Unknown to common designers.
• Standard HDL languages
• Behavioral VHDL / Verilog extension,
• SystemC extension sc_fifo, DTU (Technical
  University of Denmark) Channels,
• Do not respect delay insensitive circuit
  semantic.
• Objective
• Develop ASC, an extension to SystemC respecting
  the delay insensitive circuits semantic.

5
SystemC overview

• SystemC is a C library for modeling and
  simulate complex systems at different level of
  abstraction.
• SystemC 2.2 is an IEEE (1666) standard.
• SystemC offers access to open framework modeling.
• A SystemC model is set of hierarchical modules
  interconnected by channels.
• Each module may contain
• processes define the behavior of the
  system.
• ports communicating interface of the
  processes.
• channels interconnect the different ports
  and define their communicating
  primitives.
• internal data int, bool
• Synchronization/communication between concurrent
  processes using events.

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SystemC limitations

• Main properties of asynchronous circuits
• they use local handshaking protocols,
• they are insensitive to delays.
• Modeling asynchronous circuits with SystemC
  requires
• blocking communication channels,
• memory-less communication channels,
• immediate event notifications,
• persistent event notifications.
• Standard SystemC channels do not respect these
  features.
• Modeling Asynchronous circuits requires special
  constructs and objects not available in SystemC.

7
Outline

• Asynchronous NoC and SystemC
• Asynchronous SystemC (ASC)
• Asynchronous NoC modeling
• Conclusion

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ASC Core Language

• ASC library
• a SystemC subset for modeling asynchronous
  circuits at handshake level.
• ASC primitives for hierarchical modeling
• as_container, as_process to declare modules.
• as_push, as_pull to declare channels.
• as_activepassive_inout to declare ports.
• ASC primitives for communication and
  synchronization
• send() blocking send of data via an
  output port.
• receive() blocking receive of data via an
  input port.
• idle(port1 port2 ) waiting on a list of
  passive ports.
• nb_probe() non blocking checking by
  passive ports if a
  communication was initiated.

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Non-Determinism modeling

• Correct models of arbiters need non deterministic
  choice
• Not available in standard SystemC/C.
• ASC provides two new statementsas_choice_nd and
  as_guard.

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ASC Arbiter Example
void arbiterprocess(void) while (1)
idle(a_in1 a_in2) int l_msg 0
as_choice_nd( as_guard(a_in1.nb_probe(),
LABEL_1), as_guard(a_in2.nb_probe(),
LABEL_2)) case LABEL_1
a_in1.receive(l_msg) a_out.send(l_msg)
break case LABEL_2
a_in2.receive(l_msg) a_out.send(l_msg)
break
void consumerprocess(void) int l_msg 0
while(1) a_in.receive(l_msg) void
producer1process(void) while(1)
a_out.send(1) void producer2process(void)
while(1) a_out.send(2)
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ASC Parallel Communication

• Allow to execute several parallel communicating
  actions in the same process.
• Parallel communication actions are triggered by
  one of the following methods
• par_send for the input port,
• par_receive for the output port
• Definition of a method idle and an operator
  for synchronizing a set of parallel
  communication actions.

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ASC Parallel Consumer Example
void consumerprocess(void) while(1) int
l_msg1 0, l_msg2 0 idle(a_in1.par_receive
(l_msg1) a_in2.par_receive(l_msg2))
void producer1process(void) while(1)
this-gta_out.send(1) void producer2process(v
oid) while(1) this-gta_out.send(2)
consumerprocess
a_in2.par_receive
a_in1.par_receive
idle
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ASC Library implementation

• Add Primitive Channels as_push, as_pull
• Add Structural Elements as_process,
  as_container
• Add C constructs as_choice_nd, as_guard

Primitive Channels Signal, FIFO, Mutex, Semaphore
Structural Elements Modules, Ports, Interfaces,
Channels
Data Types 4-valued logic, Bits vectors
Event Driven Simulation Event, Processes
C language Standard
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Outline

• Asynchronous NoC and SystemC
• Asynchronous SystemC (ASC)
• Asynchronous NoC modeling
• Conclusion

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ANoC Architecture

• 2D-Mesh based Topology,
• Wormhole Packet Switching,
• Static Source Routing,
• Virtual Channel for QoS,
• Nodes and Links use QDI asynchronous logic,
• Functional units use standard synchronous logic.

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ANoC protocol

• Wormhole protocol using 34 bit width flits.
• Packet signaling
• 2 bits for signaling begin-of-packet (BOP) and
  its end (EOP).
• Static Routing using vector of dibits as path to
  the target.
• A dibit encodes the direction to follow for
  forwarding the flits of a packet.

BOP
EOP
Path to Target
Payload
BOP
EOP
Payload
33
32
31 18
17 0
33
32
31 0
Header Flit
Body Flit
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ANoC Node Architecture

• Node architecture
• 5 Input Controllers for flit routing.
• 5 Output Controllers for flit arbitration.
• Fully Decentralized Arbitration
• no global coordinator
• Fully implemented in QDI logic
• 4-phase asynchronous protocol (WCHB),
• Delay Insensitive data encoding (multi-rail),
• All data flits are 4-rail encoded (to reduce
  Power Consumption).

Asynchronous 4-rail pipeline stage
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ANoC Node ASC Model
class Process_Arbiter public as_process //
ports as_passive_inlt sc_logic gt
NEW_PACKET4 as_active_outlt sc_lvlt2gt gt
GET_PACKET // main process virtual void
process(void) while(true)
idle(NEW_PACKET0 NEW_PACKET1
NEW_PACKET2 NEW_PACKET3)
as_choice_nd( as_guard(NEW_PACKET0.nb_pr
obe(),FROM_0), as_guard(NEW_PACKET1.nb_p
robe(),FROM_1), as_guard(NEW_PACKET2.nb_
probe(),FROM_2), as_guard(NEW_PACKET3.nb
_probe(),FROM_3)) case FROM_0
NEW_PACKET0.receive()
GET_PACKET.send(0) break case
FROM_1 NEW_PACKET1.receive()
GET_PACKET.send(1) break case
FROM_2 NEW_PACKET2.receive()
GET_PACKET.send(2) break case
FROM_3 NEW_PACKET3.receive()
GET_PACKET.send(3) break

• Uses ASC SystemC library main primitives
• as_push/as_pull Communication channels.
• par_send/par_receive Parallel communication
  primitives.
• as_guard/as_choice_nd Deterministic
  Non-deterministic choices.
• ANOC node ASC model
• About 1500 lines,
• Validated using traffic generators in mixed
  level environment.

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ANoC Mixed-Level Validation

• ANOC Integration in TLM/SystemC
• Using TLM-RTL TLM-ASC transactors.
• Enable mixed-level / mixed-language
  co-simulation with
• TLM RTL ASC.

TLM
TLM- RTLIFace
NOC Synchronous Units
NOC Asynchronous Nodes
ANOC GALS architecture
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Outline

• Asynchronous NoC and SystemC
• Asynchronous SystemC (ASC)
• Asynchronous NoC modeling
• Conclusion

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Conclusion

• ASC an extension to SystemC for asynchronous
  circuits modeling
• Validated on a real asynchronous NoC
  architecture,
• Using mixed-level/mixed-language SystemC
  simulation.
• Current developments
• Specification of a model of time for ASC models,
• Implementation of trace facilities suited for
  ASC,
• Study how to perform asynchronous circuits
  synthesis from ASC/SystemC models.