ScanThroughTAP: Combining Scan Chain and Boundary Scan Features in SOC - PowerPoint PPT Presentation

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ScanThroughTAP: Combining Scan Chain and Boundary Scan Features in SOC

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What is Scan-through-TAP? ... of the internal scan chains through the ... Read scanned ready netlist with IOs. Set TAP FSM specification. Set STT specification ... – PowerPoint PPT presentation

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Title: ScanThroughTAP: Combining Scan Chain and Boundary Scan Features in SOC


1
Scan-Through-TAP Combining Scan Chain and
Boundary Scan Features in SOC
2
Introduction
  • What is Scan-through-TAP?
  • Use of IEEE Standard 1149.1 user instruction to
    concatenate the internal scan chain with the BSR
    chain to perform a single chain operation
  • What do we achieve implementing Scan-through-TAP?
  • Reduction of the scan pins number
  • Accessibility of the internal scan chains through
    the TAP controller
  • Single shift path through for burn-in and
    diagnostics
  • What kind of EDA tools do we need?
  • Standard synthesis, DFT, BSD, and ATPG tools

3
DFT/BSD in SOC Design Flow
4
Scan Insertion Flow
Read Design
  • Read in synthesized design
  • Define clock constraints
  • Define scan chain
  • Insert scan chains
  • Write out scan test protocol and netlist for
    TetraMAX

Create Test Protocol
DFT DRC
Specify Scan Architecture
Preview
Insert Scan Paths
DFT DRC Coverage
Handoff Design
5
Boundary Scan Insertion Flow
  • Read technology synthesis libraries
  • Read scanned ready netlist with IOs
  • Set TAP FSM specification
  • Set STT specification
  • Read pin map for die package BSR order
  • Preview your JTAG design
  • Insert your JTAG logic
  • Write out final netlist
  • Write BSDL file and patterns (optional)
  • Check compliance to IEEE 1149.1 STD
  • Write BSDL file and BSD patterns
  • Write the STIL protocol file for ATPG

6
Scan-Through-TAP Register
7
STT Test Patterns
8
Implementation Results (1)
  • SOC features
  • 0.25 µm CMOS technology
  • 23 mm2 of silicon area
  • 2.5 mm2 occupied by memory
  • 1 million transistors
  • 104 functional ports
  • 12 inputs
  • 44 outputs
  • 48 bidirectional
  • 5 TAP ports
  • TRST
  • TCK
  • TMS
  • TDI
  • TDO

9
Implementation Results (2)
  • Single scan register made of around 15000 scan
    flip-flops
  • Boundary scan register of 151 cell
  • 5 TAP instructions
  • BYPASS
  • EXTEST
  • PRELOAD
  • SAMPLE
  • STT
  • 32000 BSD functional test patterns
  • 1151 ATPG test patterns
  • Chip area overhead below 7
  • Caused by insertion of scan flip-flops and
    boundary scan logic
  • Combined fault coverage is slightly above 94

10
Summary
  • Scan-Through-TAP methodology provides the
    infrastructure for both testing of systems
    internal nodes and testing of systems boundary
    circuitry
  • A good solution for pin limited SOC designs
  • A middle-size processor-based SOC used for
    implementation
  • Results show small chip area overhead, acceptable
    number of test patterns, and high fault coverage
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