Title: CS/EE 362 Hardware Fundamentals Lecture 12: Designing a Single Cycle Datapath
1CS/EE 362Hardware FundamentalsLecture 12
Designing a Single Cycle Datapath
- (Chapter 5 Hennessy and Patterson)
- Winter Quarter 1998
- Chris Myers
2The Big Picture The Performance Perspective
- Performance of a machine is determined by
- Instruction count
- Clock cycle time
- Clock cycles per instruction
- Processor design (datapath and control) will
determine - Clock cycle time
- Clock cycles per instruction
- Today
- Single cycle processor
- Advantage One clock cycle per instruction
- Disadvantage long cycle time
3How to Design a Processor step-by-step
- 1. Analyze instruction set gt datapath
requirements - the meaning of each instruction is given by the
register transfers - datapath must include storage element for ISA
registers - possibly more
- datapath must support each register transfer
- 2. Select set of datapath components and
establish clocking methodology - 3. Assemble datapath meeting the requirements
- 4. Analyze implementation of each instruction to
determine setting of control points that effects
the register transfer. - 5. Assemble the control logic
4The MIPS Instruction Formats
- All MIPS instructions are 32 bits long. The
three instruction formats - R-type
- I-type
- J-type
- The different fields are
- op operation of the instruction
- rs, rt, rd the source and destination register
specifiers - shamt shift amount
- funct selects the variant of the operation in
the op field - address / immediate address offset or immediate
value - target address target address of the jump
instruction
5Step 1a The MIPS-lite Subset for today
- ADD and SUB
- addu rd, rs, rt
- subu rd, rs, rt
- OR Immediate
- ori rt, rs, imm16
- LOAD and STORE Word
- lw rt, rs, imm16
- sw rt, rs, imm16
- BRANCH
- beq rs, rt, imm16
6Logical Register Transfers
- RTL gives the meaning of the instructions
- All start by fetching the instruction
op rs rt rd shamt funct MEM PC op
rs rt Imm16 MEM PC
inst Register Transfers ADDU Rrd lt Rrs
Rrt PC lt PC 4 SUBU Rrd lt Rrs
Rrt PC lt PC 4 ORi Rrt lt Rrs
zero_ext(Imm16) PC lt PC 4 LOAD Rrt lt MEM
Rrs sign_ext(Imm16) PC lt PC 4 STORE MEM
Rrs sign_ext(Imm16) lt Rrt PC lt PC
4 BEQ if ( Rrs
Rrt ) then PC lt PC sign_ext(Imm16)
00
else PC lt PC 4
7Step 1 Requirements of the Instruction Set
- Memory
- instruction data
- Registers (32 x 32)
- read RS
- read RT
- Write RT or RD
- PC
- Extender
- Add and Sub register or extended immediate
- Add 4 or extended immediate to PC
8Step 2 Components of the Datapath
- Combinational Elements
- Storage Elements
- Clocking methodology
9Combinational Logic Elements (Basic Building
Blocks)
CarryIn
A
32
Sum
Adder
32
B
Carry
32
Select
A
32
Y
MUX
32
B
32
OP
A
32
Result
ALU
32
B
32
10Storage Element Register (Basic Building Block)
- Register
- Similar to the D Flip Flop except
- N-bit input and output
- Write Enable input
- Write Enable
- negated (0) Data Out will not change
- asserted (1) Data Out will become Data In
Write Enable
Data In
Data Out
N
N
Clk
11Storage Element Register File
RW
RA
RB
- Register File consists of 32 registers
- Two 32-bit output busses
- busA and busB
- One 32-bit input bus busW
- Register is selected by
- RA (number) selects the register to put on busA
(data) - RB (number) selects the register to put on busB
(data) - RW (number) selects the register to be
writtenvia busW (data) when Write Enable is 1 - Clock input (CLK)
- The CLK input is a factor ONLY during write
operation - During read operation, behaves as a combinational
logic block - RA or RB valid gt busA or busB valid after
access time.
Write Enable
5
5
5
busA
busW
32
32 32-bit Registers
32
busB
Clk
32
12Storage Element Idealized Memory
Write Enable
Address
- Memory (idealized)
- One input bus Data In
- One output bus Data Out
- Memory word is selected by
- Address selects the word to put on Data Out
- Write Enable 1 address selects the memoryword
to be written via the Data In bus - Clock input (CLK)
- The CLK input is a factor ONLY during write
operation - During read operation, behaves as a
combinational logic block - Address valid gt Data Out valid after access
time.
Data In
DataOut
32
32
Clk
13Clocking Methodology
Clk
Setup
Hold
Setup
Hold
Dont Care
- All storage elements are clocked by the same
clock edge - Cycle Time CLK-to-Q Longest Delay Path
Setup Clock Skew - (CLK-to-Q Shortest Delay Path - Clock Skew) gt
Hold Time
14Step 3
- Register Transfer Requirements gt Datapath
Assembly - Instruction Fetch
- Read Operands and Execute Operation
153a Overview of the Instruction Fetch Unit
- The common RTL operations
- Fetch the Instruction memPC
- Update the program counter
- Sequential Code PC lt- PC 4
- Branch and Jump PC lt- something else
Instruction Word
32
163b Add Subtract
- Rrd lt- Rrs op Rrt Example addU rd,
rs, rt - Ra, Rb, and Rw come from instructions rs, rt,
and rd fields - ALUctr and RegWr control logic after decoding
the instruction
Rs
Rt
Rd
ALUctr
RegWr
5
5
5
busA
Rw
Ra
Rb
busW
32
Result
32 32-bit Registers
ALU
32
32
busB
Clk
32
17Register-Register Timing
Clk
Clk-to-Q
New Value
Old Value
PC
Instruction Memory Access Time
Rs, Rt, Rd, Op, Func
Old Value
New Value
Delay through Control Logic
ALUctr
Old Value
New Value
RegWr
Old Value
New Value
Register File Access Time
busA, B
Old Value
New Value
ALU Delay
busW
Old Value
New Value
Rs
Rt
Rd
ALUctr
Register Write Occurs Here
RegWr
5
5
5
busA
Rw
Ra
Rb
busW
32
Result
32 32-bit Registers
ALU
32
32
Clk
busB
32
183c Logical Operations with Immediate
- Rrt lt- Rrs op ZeroExtimm16
Rt
Rd
RegDst
Mux
Rs
ALUctr
RegWr
5
5
5
busA
Rw
Ra
Rb
busW
Result
32
32 32-bit Registers
ALU
32
32
busB
Clk
32
Mux
ZeroExt
imm16
32
16
ALUSrc
193d Load Operations
- Rrt lt- MemRrs SignExtimm16 Example lw
rt, rs, imm16
Rt
Rd
RegDst
Mux
Rs
ALUctr
RegWr
5
5
5
busA
W_Src
Rw
Ra
Rb
busW
32
32 32-bit Registers
ALU
32
32
busB
Clk
MemWr
32
Mux
Mux
WrEn
Adr
Data In
32
Data Memory
Extender
32
imm16
32
16
Clk
ALUSrc
ExtOp
203e Store Operations
- Mem Rrs SignExtimm16 lt- Rrt Example
sw rt, rs, imm16
Rt
Rd
ALUctr
MemWr
W_Src
RegDst
Mux
Rs
Rt
RegWr
5
5
5
busA
Rw
Ra
Rb
busW
32
32 32-bit Registers
ALU
32
32
busB
Clk
32
Mux
Mux
WrEn
Adr
Data In
32
32
Data Memory
Extender
imm16
32
16
Clk
ALUSrc
ExtOp
213f The Branch Instruction
- beq rs, rt, imm16
- memPC Fetch the instruction from memory
- Equal lt- Rrs Rrt Calculate the branch
condition - if (COND eq 0) Calculate the next instructions
address - PC lt- PC 4 ( SignExt(imm16) x 4 )
- else
- PC lt- PC 4
22Datapath for Branch Operations
- beq rs, rt, imm16 Datapath generates
condition (equal)
Inst Address
nPC_sel
32
00
imm16
PC Ext
23Putting it All Together A Single Cycle Datapath
Instructionlt310gt
lt2125gt
lt1620gt
lt1115gt
lt015gt
Imm16
Rd
Rt
Rs
RegDst
ALUctr
MemtoReg
MemWr
nPC_sel
Equal
Rt
Rd
0
1
Rs
Rt
4
RegWr
5
5
5
busA
Rw
Ra
Rb
busW
00
32
32 32-bit Registers
ALU
0
32
busB
32
0
PC
32
Mux
Mux
Clk
32
WrEn
Adr
1
Clk
1
Data In
Extender
Data Memory
imm16
PC Ext
32
16
imm16
Clk
ExtOp
ALUSrc
24Summary
- 5 steps to design a processor
- 1. Analyze instruction set gt datapath
requirements - 2. Select set of datapath components establish
clock methodology - 3. Assemble datapath meeting the requirements
- 4. Analyze implementation of each instruction to
determine setting of control points that effects
the register transfer. - 5. Assemble the control logic
- MIPS makes it easier
- Instructions same size
- Source registers always in same place
- Immediates same size, location
- Operations always on registers/immediates
- Single cycle datapath gt CPI1, CCT gt long
- Next time implementing control