RF Front End Design Considerations for WLAN Systems

1
RF Front End Design Considerations for WLAN
Systems

• Subhashish Mukherjee
• Texas Instruments

2
Agenda

• 802.11 WLAN Overview
• Standards 802.11b, 802.11a, 802.11g
• Receive Architecture
• Transmit Architecture
• Local Oscillator
• Power Amplifier
• Process

3
802.11 Infrastructure vs. ad-hoc networks
infrastructure network
AP Access Point
AP
AP
wired network
AP
ad-hoc network
4
Wireless Technology Matrix
5
802.11b - broad overview

• Frequency 2400MHz - 2484MHz
• Time Division Duplexed system
• Direct sequence spread spectrum
• Each channel about 16MHz wide
• Channel allocation as shown below
• Different standard in US and Europe complicates
  LO and Filter Designs

US
European
6
11b Top level TX specs
TX mask

• Tx Power Level 30dBm Max
• Modulation QPSK
• Carrier Suppression 15dB below the sinx/x peak.
• PAR 5dB

7
11b Adjacent channel rejection

• Per the standard, adjacent channel rejection is
  to be met with only one adjacent channel as shown
  in figure below. This is mainly a spec of IIP2 of
  the receiver and LO phase noise.
• To estimate IIP3, we assume 2 adjacent channels
  32dB above the desired channel.

8
802.11a
11a - TX mask
PAR 14dB

• 11a - channel allocation

9
802.11a
10
Receiver Architecture Choices

• Heterodyne
• Low IF
• Direct Conversion
• Direct Sampling
• .

11
Heterodyne Receiver
12
Low IF receiver
13
Spectrum analysis for low IF arch
For channel frequency 2400MHz
14
Spectrum analysis for low IF arch
For channel frequency 2500MHz
15
Direct conversion receiver
16
Spectrum analysis for direct conversion arch
For channel frequency 2400MHz
17
Direct Sampling Receiver

• Same concept as direct conversion.
• Difference being conversion of the IF filter to
  switch cap domain.
• This needs an Anti-alias filter.

I

• Disadvantages/Concerns
• Matching requirement for the clock skew .
• Systematic jitter on the sampling and dump
  switch
• Presence of nearby blockers , make the instant
  when the sampling switch turns off , signal
  dependent

Q
18
Comparison of architectures
Direct conversion
Low IF

• IF filter complexity
• Filter bandwidth
• ADC clock rate
• IF chain power consumption area
• Image frequency folding back
• dc offset due to LO self mixing
• Even order distortion
• Flicker noise

• Less
• Less
• Less
• Less
• No problem
• Yes
• Yes
• Yes

• More
• Twice
• More
• More
• More problem
• No problem
• Less problem
• Less problem

• Direct conversion architecture is becoming
  popular because 1) Low power and area in IF
  chain
• 2) Problem of image frequency rejection puts more
  constraint on pre-selector filter in Low IF
  architecture

19
How do we tackle 1/f noise

• Capacitive coupling between LNA and Mixer to
  avoid flicker due to LNA .
• Increase the length and width of the transistors
  for the baseband cells (after the mixer)
• Flicker noise due to the driver transistor gets
  translated to LO freq.
• Flicker contribution due to the Mixer LO
  switches is further reduced by biasing at higher
  current .
• AC coupling from mixer o/p to Filter.
• References -
• Noise in Current-Commuting CMOS Mixers (JSSC,
  June 99)
• An Analysis of Flicker Noise rejection in Low
  Power and Low Voltage CMOS Mixers (JSSC January
  2001)
• Noise in RF-CMOS Mixers A Simple Physical
  Model (JSSC January 2000)

20
d-c rejection in IF stages

• The issue
• An unwanted d-c component is generated at mixer
  output due to the LO self-mixing which can
  saturate the amps upon gain-up
• Two approaches for dc rejection
• 1) a-c coupling the mixer output and intermediate
  stages
• 2) d-c Subtraction Estimate the dc content in
  the signal and then subtract it at the mixer
  output. This estimation can be done after the ADC
  in the digital domain and can be converted back
  to analog using a DAC.

21
LO leakage and reverse isolation

• LO leakage happens due to coupling between the
  LO to the LNA output . This is transmitted back
  to antenna by the reverse transfer function of
  LNASwitchFilter .
• Strategy to counter
• Truly differential scheme of mixers directly
  reduce the peak of average coupling .
• Provide cascode in the LNA to improve the reverse
  isolation .

22
Even order inter-mod distortion

• Two strong interferers close to the desired
  channel experience a non-linearity
  in the LNA .
• If then
  y(t) contains the term
• which is
  the low-freq. even order distortion .
• In reality , mixer has a finite direct
  feedthrough from RF input to the Mixer output .
  (This is caused by Tx. Mismatch , and duty cycle
  mismatches )

• Reference Design Considerations for Direct
  Conversion Receivers by Behzad Razavi , JSSC
  June 1997

23
Choice of filtering and ADC sampling rate
Example Euro, 44MHz ADC, 3rd. Order Cheby
Filter.
24
Choice of filtering and ADC sampling rate
Example Euro, 44MHz ADC, 3rd. Order Cheby
Filter.
25
TX Direct Up-conversion
26
Tx Direct modulation
27
Choice of TX architecture

• The main problems with direct modulation
  architecture are
• Phase modulation in the DCO and amplitude
  modulation in the PA requires precise
  synchronization
• 11b has a bandwidth of about 16MHz which is too
  high for amplitude modulation of PA through power
  supply

28
TX Filtering and DAC sampling rate
44 MHz DAC Output for Tx Mask with Rolloff of 0.6
DAC Output Filtered by 3rd Order Chebyshev Filter
29
Tx DAC Resolution

• The DAC resolution is determined by the standard
  TX Mask requirement. The DACFilter noise floor
  should be 30dB below signal till 22MHz and 50dB
  below beyond.
• For a DAC sampling at 44MHz (2X oversampling), a
  4.3 ENOB DAC meets the -30dBr Mask. The -50dB
  Mask is achieved with the following filter.
• A 6 Bit DAC with 5 Bit ENOB will suffice with
  margin.
• Following figures show a case where DAC noise
  floor is exactly -30dB below, filtered by a 3rd.
  Order Chebyshev filter.
• This may need modification after taking into
  account spectral re-growth in PA and the adjacent
  channel interference limit.

30
A WLAN Analog Front End
DATA
3-5 dB Loss
31
Required LO specs

• Phase noise specs
• Out-of-band phase noise
• LO phase noise beats with the adjacent channel
  and folds in-band. This causes a degradation in
  the SNR and causes the threshold to degrade.
• We want this noise 20dB below the threshold
  signal power. Also we want to make the system
  tolerant to an adjacent channel power 35dB above.
• The bandwidth of the system 16MHz
• Adjacent channel offset 25MHz
• L Average LO phase noise density between 17MHz
  and 33MHz offset
• L 10log(16MHz) 35 -20
• L -127dBc/Hz

32
LO synthesizer architecture
Threshold detection and digital acquisition
Program
4
Programmable
Divider
LO 2X 2412MHz
Reference
PFD
R
VCO
Clock fRMhz
2
CP
Loop Filter
1 MHz
2
Program?
N2412 to 2484
10 bits
Main
N/N1
Divider
2412-2484MHz
Program
10 bits
Swallow
Divider
Program
33
Power Amplifier
34
Power Amplifier
35
Power Amplifier
36
Power Amplifier Power Backoff
37
Choice of Process SiGe vs CMOS
38
Integrated Inductor
39
Q A