Title: EET 3350 Digital Systems Design Textbook: John Wakerly Chapter 8: 8'2
1EET 3350 Digital Systems Design Textbook John
Wakerly Chapter 8 8.2
2Agenda for Today
- Latches and Flip-Flops
- VHDL representations
- SSI latches and Flip-Flops
- Latch and Flip-Flop Applications
- Multibit Latches and Registers
- MSI registers
- Register Applications
- Register Transfer Language
- CPU Components
- Microprocessor Organization
3Latches and Flip-Flops
- Using VHDL to describe and simulate latches
- SSI Latches and Flip-Flops
4Latches and Flip-Flops
- In the same way that gates are the building
blocks of combinational circuits, latches and
flip-flops are the building blocks of sequential
circuits. - Gates had to be built directly from transistors,
latches can be built from gates, and flip-flops
can be built from latches. - The difference between a latch and a flip-flop is
that a latch does not have a clock signal,
whereas a flip-flop always does.
5D Flip-Flop
- NAND circuit, symbol and characteristic table
6D Flip-Flop
- VHDL for a D Flip-Flop using NAND gates
library IEEE use IEEE.std_logic_1164.all entity
Vdlatch is port (D, C in STD_LOGIC
Q, QN buffer STD_LOGIC ) end Vdlatch --
structural architecture for D latch architecture
Vdlatch_s of Vdlatch is signal DN, SN, RN
STD_LOGIC component inv port (I in STD_LOGIC
O out STD_LOGIC ) end component
component nand2b port (I0, I1 in STD_LOGIC O
buffer STD_LOGIC ) end component begin
U1 inv port map (D,DN) U2 nand2b port map
(D,C,SN) U3 nand2b port map (C,DN,RN) U4
nand2b port map (SN,QN,Q) U5 nand2b port map
(Q,RN,QN) end Vdlatch_s
7D Flip-Flop
- VHDL for a D Flip-Flop using NAND gates
library IEEE use IEEE.std_logic_1164.all entity
Vdlatch is port (D, C in STD_LOGIC
Q, QN out STD_LOGIC ) end Vdlatch --
structural architecture for D latch architecture
Vdlatch_s2 of Vdlatch is signal DN, SN, RN, IQ,
IQN STD_LOGIC component inv port (I in
STD_LOGIC O out STD_LOGIC ) end
component component nand2 port (I0, I1 in
STD_LOGIC O out STD_LOGIC ) end
component begin U1 inv port map (D,DN) U2
nand2 port map (D,C,SN) U3 nand2 port map
(C,DN,RN) U4 nand2 port map (SN,IQN,IQ)
U5 nand2 port map (IQ,RN,IQN) Q lt IQ QN lt
IQN end Vdlatch_s2
8D Flip-Flop
- VHDL behavioral architecture
library IEEE use IEEE.std_logic_1164.all entity
Vdlatch is port (D, C in STD_LOGIC
Q, QN buffer STD_LOGIC ) end Vdlatch --
behavioral architecture for a D
latch architecture Vdlatch_b of Vdlatch
is begin process(C, D, Q) begin if (C'1')
then Q lt D end if QN lt not Q end
process end Vdlatch_b
9D Flip-Flop
- VHDL behavioral model for a D Flip-Flop
library IEEE use IEEE.std_logic_1164.all entity
Vdff is port (D, CLK in STD_LOGIC Q
out STD_LOGIC ) end Vdff -- behavioral model
of an edge-triggered D flip-flop architecture
Vdff_b of Vdff is begin process(CLK) begin
if (CLK'event and CLK'1') then Q lt D end if
end process end Vdff_b
10Integrated Circuits
- Common digital components are available in
Integrated Circuits (IC) packages - ICs can be divided into groups based on the
number of gates (or equivalent) per device
11Small Scale Integration
- Many types of latches and Flip-Flops are
available in SSI packages - DIP - Come with 1, 2 or 4 copies per package (number of
I/O pins is the limitation here) - Well look at some of the more commonly used
devices
12Datasheets
- Manufacturers datasheets for SSI/MSI
- Datasheets include everything a designer needs
- truth table
- logic symbol
- pin names/assignments
- circuit
- timing diagrams
- electrical parameters
13Part Numbers
- part numbers for 7400 series logic devices often
use the following naming convention
SN 74 ALS 245 A
package type, quality grade, etc. (varies widely
by manufacturer)
manufacturer
temperature range
logic subfamily
device
LS - Low Power Schottky AS - Advanced Schottky
ALS - Advanced Low Power Schottky
SN Texas Instruments DM Fairchild
74 - commercial 54 military (extended)
hundreds of different devices in each family
14SSI Flip-Flops
- 74LS74 dual edge-triggered D-type Flip-Flops
15SSI Flip-Flop
- 74LS74 dual edge-triggered D-type Flip-Flops
- Each flip-flop has individual clear and set
inputs, and also complementary Q and Q outputs
16D Flip-Flop
- VHDL for a D Flip-Flop with Preset and Clear
library IEEE use IEEE.std_logic_1164.all entity
Vdff74 is port (D, CLK, PR_L, CLR_L in
STD_LOGIC Q, QN out STD_LOGIC ) end
Vdff74 architecture Vdff74_b of Vdff74
is signal PR, CLR STD_LOGIC begin process(CLR_L,
CLR, PR_L, PR, CLK) begin PR lt not PR_L
CLR lt not CLR_L if (CLR and PR) '1' then
Q lt '0' QN lt '0' elsif CLR '1' then Q
lt '0' QN lt '1' elsif PR '1' then Q lt
'1' QN lt '0' elsif (CLK'event and CLK
'1') then Q lt D QN lt not D end if end
process end Vdff74_b
17SSI JK Flip-Flop
- The 74LS109 consists of two completely
independent transition clocked JK Flip-Flops
18SSI JK Flip-Flop
- 74LS109 clocked JK Flip-Flops
19SSI D Latch
- 74LS375 is a 4-Bit D-Type Latch
20SSI D Latch
- 74LS375 4-Bit D-Type Latch
- When the Enable (E) is HIGH, information present
at the D input will be transferred to the Q
output and, if E is HIGH, the Q output will
follow the input. - When E goes LOW, the information present at the D
input prior to its setup time will be retained at
the Q outputs.
21SSI Flip-Flop Application
- Using a 74LS375 for the memory of a 16-state (or
fewer) sequential machine
22Multibit Latches and Registers
- Registers
- Shift Registers
23Multibit Latches and Registers
- Register
- a register is simply a collection of latches or
flip-flops that work together to handle multibit
binary data - working together means they have a common clock
- an n-bit register is a collection of n D
flip-flops with a common clock used to store n
related bits - Common register types
- Multi-port
- Shift
- Universal
24Multibit Registers
- Typical register packages include
- Quad register gt 4 D flip-flops with common clock
- Octal register gt 8 D flip-flops with common
clock - Hex register gt 16 D flip-flops with common clock
- Typical Signals include
- CLR_L gt asynchronous, active-low, clear signal
- Examples of common MSI registers include
- 74x175 Quad D Flip-Flop
- 74x374 Octal D Flip-Flop
- 74x273 Octal D Flip-Flop with Clear
- 74x373 Octal Transparent Latch with 3-State
Outputs - 74x377 Octal D Flip-Flop with Enable
25Multibit Latches and Registers
- Various types of registers are available
commercially - The simplest register is one that consists of
only flip-flops without any gates - A generalized quad D flip-flop register is shown
- inputs, Ii
- outputs, Ai
26Multibit Latches and Registers
- The commercially available 74LS175 is a simple
Quad D Flip-Flop register - The 74LS175 datasheet (Motorola) includes the
following
16-pin DIP
27Multibit Latches and Registers
- The 74LS175 has
- edge-triggered D-Type inputs
- asynchronous common reset (CLR or MR), active low
- true and complement (inverted) outputs
28Multibit Latches and Registers
- The logic symbol and circuit diagram for the
74LS175 illustrate the major features
29Multibit Latches and Registers
- The circuit for the 74x175 that is found in your
book appears at right
30Multibit Latches and Registers
- 74LS374 Octal D-type Flip-Flop
Requires a 20-pin DIP
31Multibit Latches and Registers
- 74LS374 Octal D-type Flip-Flop
only the Q outputs are available due to limited
number of I/O pins
32Multibit Latches and Registers
- 74LS374 Octal D-type Flip-Flop
The 74LS374 has separate D-type inputs for each
flip-flop and 3-state outputs for bus oriented
applications. A buffered Clock (CP) and Output
Enable (OE) is common to all flip-flops.
33Multibit Latches and Registers
- 74LS374
- 8-bit (octal) register
- 3-state output
34Octal Register
- 8-bit register with asynchronous reset
library ieee use ieee.std_logic_1164.all
entity reg8 is port ( d in
std_logic_vector(7 downto 0) resetn,
clock in std_logic q
out std_logic_vector(7 downto 0) ) end
reg8 architecture behavior of reg8 is Begin
process ( resetn, clock ) begin if
resetn '0' then q lt "00000000"
elsif (clock'event and clock '1) then
q lt d end if end process end
behavior
35Hex Register
library IEEE use IEEE.std_logic_1164.all entity
Vreg16 is port (CLK, CLKEN, OE_L, CLR_L in
STD_LOGIC D in STD_LOGIC_VECTOR(1 to
16) -- Input bus Q out
STD_ULOGIC_VECTOR(1 to 16) -- Output bus
(three-state) ) end Vreg16 architecture
Vreg16 of Vreg16 is signal CLR, OE STD_LOGIC
-- active-high versions of signals signal IQ
STD_LOGIC_VECTOR(1 to 16) -- internal Q
signals begin process(CLK, CLR_L, CLR, OE_L, OE,
IQ) begin CLR lt not CLR_L OE lt not
OE_L if (CLR '1') then IQ lt (others gt
'0') elsif (CLK'event and CLK'1') then
if (CLKEN'1') then IQ lt D end if end
if if OE '1' then Q lt To_StdULogicVector(I
Q) else Q lt (others gt 'Z') end if end
process end Vreg16
36Octal Register
- 74LS273 octal D Flip-Flop with Clear
Requires a 20-pin DIP
37Octal Register
- 74LS273 octal D Flip-Flop with Clear
buffered outputs
38Other Octal Registers
- 74LS273
- clock (CP) timing
39Octal Registers
- 74LS273
- asynchronous clear (MR)
asynchronous
40Octal Registers
- 74LS373 Octal Transparent Latch with 3-State
Outputs
41Octal Registers
42Octal Registers
- 74LS373 Octal Latch
- The flip-flops appear transparent to the data
(data changes asynchronously) when Latch Enable
(LE) is HIGH. - When LE is LOW, the data that meets the setup
times is latched. - Data appears on the bus when the Output Enable
(OE) is LOW. - When OE is HIGH the bus output is in the high
impedance state.
43Octal Latch
- 74LS377 Octal D Flip-Flop with Enable
44Octal Latch
- 74LS377 Octal D Flip-Flop with Enable
This register consists of eight D-type flip-flops
with a buffered common clock and a buffered
common clock enable.
45Other Latch
46Octal Latch
47Mulitbit Registers
- Common Register Uses
- temporary data storage and transfer
- parallel-to-serial and serial-to-parallel
conversion - data manipulation (complementation, rotation,
etc.) - Registers are central to the design of modern
processors - instruction register
- operands, accumulators
- faster and more convenient than main memory
- more or larger registers can help speed up
complex calculations
48Register Applications
- Register Transfer Language
- Microprocessors / CPUs
49Register Transfer Language
- Earlier this semester we looked at a hierarchy of
levels for digital systems - Just above our current level is the Register
Transfer Level
50Register Transfer Level
- The movement of data stored in registers and the
processing performed on the data are referred to
as Register Transfer Operations - The Register Transfer Language (RTL) can be used
to specify register transfers and the components
of - the registers within the system
- the operations performed on system data
- the control that defines the sequence of
operations
51Microoperations
- Each register has a set of elementary operations
it can do - e.g., load, increment, shift, etc.
- The combination of elementary register operations
and combinational functions define simple system
operations - These are the microoperations of the system
- usually performed in a single clock cycle
- sequence of ?-ops specified by control unit
52Register Transfer Operations
- The microoperations are generally classified into
four types - Transfer - moving data from register to register
- Arithmetic - signed and unsigned arithmetic
- Logical - bitwise AND, OR, NOT, etc.
- Shift - shifts, rotates, etc.
53Register Transfer Language
- Registers denoted by upper case letters, and
optionally followed by digits or letters - Register transfer operations the movement of
data stored in registers and the processing
performed on the data
54Register Transfer Language
- Describe how data is transferred
registers/memory - Can easily translate to VHDL for implementation
55Register Transfer Language
- Register Transfer Language (RTL) used to
describe CPU organization in high-level terms - RTL expressions are made up of elements which
describe the registers being manipulated, and the
micro-ops being performed on them - Here are the basic components of RTL expressions
56Register Transfer Language
- a step below assembly language
57Microcomputer Architecture
- Micrcomputer organization, without peripherals
58Microprocessor Architecture
- The 8086/8088 has two separate internal units,
the EU and the BIU
59Microprocessor Architecture
60Microprocessor Architecture
61Microprocessor Architecture
- The status and control flags
62Microprocessor Architecture
- Registers for the Intel processors from 8086/8088
through Pentium
63RTL and Microprocessors
- RTL can be used to design the manner in which the
instruction set is executed
RTL represents a further level of abstraction for
the designer
64Assignments