Modeling of Circuits with a Regular Structure Mixing Design Styles Synthesis

1
Modeling of Circuits with a RegularStructureM
ixing Design StylesSynthesis
ECE 448 Lecture 12
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Required reading

• S. Brown and Z. Vranesic, Fundamentals of
  Digital Logic with VHDL Design
• Chapter 6.6.4, Generate Statements
• Chapter A.7.5, Generate Statement
• Chapter A.10.9, Using Subcircuits with Generic
• Parameters
• Chapter A.11, Common Errors in VHDL Code

3
Generate scheme for equations
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Data-flow VHDL
Major instructions
Concurrent statements

• concurrent signal assignment (?)
• conditional concurrent signal assignment
• 
  (when-else)
• selected concurrent signal assignment
• 
  (with-select-when)
• generate scheme for equations
• 
  (for-generate)

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For Generate Statement
For - Generate
label FOR identifier IN range GENERATE
BEGIN Concurrent Statements
END GENERATE
6
PARITY Example
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PARITY Block Diagram
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PARITY Entity Declaration

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• ENTITY parity IS
• PORT(
• parity_in IN STD_LOGIC_VECTOR(7 DOWNTO
  0)
• parity_out OUT STD_LOGIC
• )
• END parity

9
PARITY Block Diagram
xor_out(2)
xor_out(3)
xor_out(4)
xor_out(5)
xor_out(6)
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PARITY Architecture

• ARCHITECTURE parity_dataflow OF parity IS
• SIGNAL xor_out std_logic_vector (6 downto 1)
• BEGIN
• xor_out(1) lt parity_in(0) XOR parity_in(1)
• xor_out(2) lt xor_out(1) XOR parity_in(2)
• xor_out(3) lt xor_out(2) XOR parity_in(3)
• xor_out(4) lt xor_out(3) XOR parity_in(4)
• xor_out(5) lt xor_out(4) XOR parity_in(5)
• xor_out(6) lt xor_out(5) XOR parity_in(6)
• parity_out lt xor_out(6) XOR parity_in(7)
• END parity_dataflow

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PARITY Block Diagram (2)
xor_out(2)
xor_out(3)
xor_out(4)
xor_out(5)
xor_out(6)
xor_out(7)
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PARITY Architecture

• ARCHITECTURE parity_dataflow OF parity IS
• SIGNAL xor_out STD_LOGIC_VECTOR (7 downto 0)
• BEGIN
• xor_out(0) lt parity_in(0)
• xor_out(1) lt xor_out(0) XOR parity_in(1)
• xor_out(2) lt xor_out(1) XOR parity_in(2)
• xor_out(3) lt xor_out(2) XOR parity_in(3)
• xor_out(4) lt xor_out(3) XOR parity_in(4)
• xor_out(5) lt xor_out(4) XOR parity_in(5)
• xor_out(6) lt xor_out(5) XOR parity_in(6)
• xor_out(7) lt xor_out(6) XOR parity_in(7)
• parity_out lt xor_out(7)
• END parity_dataflow

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PARITY Architecture (2)

• ARCHITECTURE parity_dataflow OF parity IS
• SIGNAL xor_out STD_LOGIC_VECTOR (7 DOWNTO 0)
• BEGIN
• xor_out(0) lt parity_in(0)
• G2 FOR i IN 1 TO 7 GENERATE
• xor_out(i) lt xor_out(i-1) XOR parity_in(i)
• END GENERATE G2
• parity_out lt xor_out(7)
• END parity_dataflow

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Generate scheme for components
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Structural VHDL
Major instructions

• component instantiation (port map)
• component instantiation with generic
• 
  (generic map, port map)
• generate scheme for component instantiations
• 
  (for-generate)

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Example 1
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Example 1
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A 4-to-1 Multiplexer

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• ENTITY mux4to1 IS
• PORT ( w0, w1, w2, w3 IN STD_LOGIC
• s IN STD_LOGIC_VECTOR(1 DOWNTO 0)
• f OUT STD_LOGIC )
• END mux4to1
• ARCHITECTURE Dataflow OF mux4to1 IS
• BEGIN
• WITH s SELECT
• f lt w0 WHEN "00",
• w1 WHEN "01",
• w2 WHEN "10",
• w3 WHEN OTHERS
• END Dataflow

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Straightforward code for Example 1

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• ENTITY Example1 IS
• PORT ( w IN STD_LOGIC_VECTOR(0 TO 15)
• s IN STD_LOGIC_VECTOR(3 DOWNTO 0)
• f OUT STD_LOGIC )
• END Example1

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Straightforward code for Example 1

• ARCHITECTURE Structure OF Example1 IS
• COMPONENT mux4to1
• PORT ( w0, w1, w2, w3 IN STD_LOGIC
• s IN STD_LOGIC_VECTOR(1 DOWNTO 0)
• f OUT STD_LOGIC )
• END COMPONENT
• SIGNAL m STD_LOGIC_VECTOR(0 TO 3)
• BEGIN
• Mux1 mux4to1 PORT MAP ( w(0), w(1), w(2),
  w(3), s(1 DOWNTO 0), m(0) )
• Mux2 mux4to1 PORT MAP ( w(4), w(5), w(6),
  w(7), s(1 DOWNTO 0), m(1) )
• Mux3 mux4to1 PORT MAP ( w(8), w(9),
  w(10), w(11), s(1 DOWNTO 0), m(2) )
• Mux4 mux4to1 PORT MAP ( w(12), w(13), w(14),
  w(15), s(1 DOWNTO 0), m(3) )
• Mux5 mux4to1 PORT MAP ( m(0), m(1), m(2),
  m(3), s(3 DOWNTO 2), f )
• END Structure

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Modified code for Example 1

• ARCHITECTURE Structure OF Example1 IS
• COMPONENT mux4to1
• PORT ( w0, w1, w2, w3 IN STD_LOGIC
• s IN STD_LOGIC_VECTOR(1 DOWNTO 0)
• f OUT STD_LOGIC )
• END COMPONENT
• SIGNAL m STD_LOGIC_VECTOR(0 TO 3)
• BEGIN
• G1 FOR i IN 0 TO 3 GENERATE
• Muxes mux4to1 PORT MAP (
• w(4i), w(4i1), w(4i2), w(4i3), s(1
  DOWNTO 0), m(i) )
• END GENERATE
• Mux5 mux4to1 PORT MAP ( m(0), m(1), m(2), m(3),
  s(3 DOWNTO 2), f )
• END Structure

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Example 2
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Example 2
w
y
w
y
0
0
0
0
y
w
w
y
1
1
1
1
y
y
2
2
y
y
En
3
3
w
y
y
0
0
4
w
y
y
1
1
5
y
y
2
6
w
w
y
y
y
2
En
3
0
0
7
w
y
w
1
1
3
y
2
w
y
y
w
y
En
En
8
0
0
3
w
y
y
1
1
9
y
y
2
10
y
y
En
3
11
y
w
y
0
0
12
y
w
y
1
1
13
y
y
2
14
y
y
En
3
15
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A 2-to-4 binary decoder

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• ENTITY dec2to4 IS
• PORT ( w IN STD_LOGIC_VECTOR(1 DOWNTO 0)
• En IN STD_LOGIC
• y OUT STD_LOGIC_VECTOR(0 TO 3) )
• END dec2to4
• ARCHITECTURE Dataflow OF dec2to4 IS
• SIGNAL Enw STD_LOGIC_VECTOR(2 DOWNTO 0)
• BEGIN
• Enw lt En w
• WITH Enw SELECT
• y lt "1000" WHEN "100",
• "0100" WHEN "101",
• "0010" WHEN "110",
• "0001" WHEN "111",
• "0000" WHEN OTHERS

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VHDL code for Example 2 (1)

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• ENTITY dec4to16 IS
• PORT (w IN STD_LOGIC_VECTOR(3 DOWNTO 0)
• En IN STD_LOGIC
• y OUT STD_LOGIC_VECTOR(0 TO 15) )
• END dec4to16

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VHDL code for Example 2 (2)

• ARCHITECTURE Structure OF dec4to16 IS
• COMPONENT dec2to4
• PORT ( w IN STD_LOGIC_VECTOR(1 DOWNTO 0)
• En IN STD_LOGIC
• y OUT STD_LOGIC_VECTOR(0 TO 3) )
• END COMPONENT
• SIGNAL m STD_LOGIC_VECTOR(0 TO 3)
• BEGIN
• G1 FOR i IN 0 TO 3 GENERATE
• Dec_ri dec2to4 PORT MAP ( w(1 DOWNTO 0), m(i),
  y(4i TO 4i3) )
• END GENERATE
• Dec_left dec2to4 PORT MAP ( w(3 DOWNTO 2), En,
  m )
• END Structure

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Example 3 Variable Rotator
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Example 3 Variable rotator - Interface
A
16
4
B
A ltltlt B
16
C
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Block diagram
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VHDL code for a 16-bit 2-to-1 Multiplexer
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY mux2to1_16 IS PORT ( w0 IN
STD_LOGIC_VECTOR(15 DOWNTO 0) w1 IN
STD_LOGIC_VECTOR(15 DOWNTO 0) s
IN STD_LOGIC f OUT STD_LOGIC_VECTOR(15
DOWNTO 0) ) END mux2to1_16 ARCHITECTURE
dataflow OF mux2to1_16 IS BEGIN f lt w0 WHEN s
'0' ELSE w1 END dataflow
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Fixed rotation

• a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8)
  a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0)
• a(12) a(11) a(10) a(9) a(8) a(7) a(6)
  a(5) a(4) a(3) a(2) a(1) a(0) a(15) a(14)
  a(13)

ltltlt 3
y lt a(12 downto 0) a(15 downto 13)
a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8)
a(7) a(6) a(5) a(4) a(3) a(2) a(1)
a(0) a(10) a(9) a(8) a(7) a(6) a(5)
a(4) a(3) a(2) a(1) a(0) a(15) a(14) a(13)
a(12) a(11)
ltltlt 5
y lt a(10 downto 0) a(15 downto 11)
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Fixed rotation by L positions

• a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8)
  a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0)
• a(15-L) a(15-L-1) . . . . . . . . . . . . . .
  a(1) a(0) a(15) a(14) . . . . . . . a(15-L2)
  a(15-L1)

ltltlt L
y lt a(15-L downto 0) a(15 downto 15-L1)
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VHDL code forfor a fixed 16-bit rotator
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY fixed_rotator_left_16 IS GENERIC ( L
INTEGER 1) PORT ( a IN STD_LOGIC_VECTOR(15
DOWNTO 0) y OUT STD_LOGIC_VECTOR(15 DOWNTO
0) ) END fixed_rotator_left_16 ARCHITECTURE
dataflow OF fixed_rotator_left_16 IS BEGIN y
lt a(15-L downto 0) a(15 downto 15-L1) END
dataflow
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Structural VHDL code forfor a variable 16-bit
rotator (1)
LIBRARY ieee USE ieee.std_logic_1164.all
ENTITY variable_rotator_16 is PORT( A
IN STD_LOGIC_VECTOR(15 downto 0) B IN
STD_LOGIC_VECTOR(3 downto 0) C OUT
STD_LOGIC_VECTOR(15 downto 0) ) END
variable_rotator_16
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Structural VHDL code forfor a variable 16-bit
rotator (2)
LIBRARY ieee USE ieee.std_logic_1164.all
ARCHITECTURE structural OF variable_rotator_16
IS COMPONENT mux2to1_16 PORT ( w0 IN
STD_LOGIC_VECTOR(15 DOWNTO 0) w1 IN
STD_LOGIC_VECTOR(15 DOWNTO 0) s
IN STD_LOGIC f OUT STD_LOGIC_VECTOR(15
DOWNTO 0) ) END COMPONENT COMPONENT
fixed_rotator_left_16 GENERIC ( L INTEGER
1) PORT ( a IN STD_LOGIC_VECTOR(15 DOWNTO
0) y OUT STD_LOGIC_VECTOR(15 DOWNTO 0) )
END COMPONENT
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Structural VHDL code forfor a variable 16-bit
rotator (3)
TYPE array1 IS ARRAY (0 to 4) OF
STD_LOGIC_VECTOR(15 DOWNTO 0) TYPE array2 IS
ARRAY (0 to 3) OF STD_LOGIC_VECTORS(15 DOWNTO
0) SIGNAL Al array1 SIGNAL Ar
array2 BEGIN Al(0) lt A G FOR i IN 0 TO 3
GENERATE ROT_I fixed_rotator_left_16
GENERIC MAP (L gt 2 i) PORT MAP ( a gt Al(i)
, y gt Ar(i)) MUX_I mux2to1_16
PORT MAP (w0 gt Al(i), w1 gt Ar(i),
s gt B(i), f gt Al(i1)) END
GENERATE C lt Al(4) END variable_rotator_16
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Constants
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Constants

• Syntax
• CONSTANT name type value
• Examples
• CONSTANT init_value STD_LOGIC_VECTOR(3 downto
  0) "0100"
• CONSTANT ANDA_EXT STD_LOGIC_VECTOR(7 downto 0)
  X"B4"
• CONSTANT counter_width INTEGER 16
• CONSTANT buffer_address INTEGER 16FFFE
• CONSTANT clk_period TIME 20 ns
• CONSTANT strobe_period TIME 333.333 ms

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Constants - features

• Constants can be declared in a
• PACKAGE, ENTITY, ARCHITECTURE
• When declared in a PACKAGE, the constant
• is truly global, for the package can be used
• in several entities.
• When declared in an ARCHITECTURE, the
• constant is local, i.e., it is visible only
  within this architecture.
• When declared in an ENTITY declaration, the
  constant
• can be used in all architectures associated with
  this entity.

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Packages
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Explicit Component Declaration versus Package

• Explicit component declaration is when you
  declare components in main code
• When have only a few component declarations, this
  is fine
• When have many component declarations, use
  packages for readability
• Packages also help with portability and sharing
  of libraries among many users in a company
• Remember, the actual instantiations always take
  place in main code
• Only the declarations can be in main code or
  package

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Explicit Component Declaration Tips

• For simple projects put entity .vhd files all in
  same directory
• Declare components in main code
• If using Aldec, make sure compiler knows the
  correct hierarchy
• From lowest to highest
• Xilinx will figure out hierarchy automatically

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METHOD 2 Package component declaration

• Components declared in package
• Actual instantiations and port maps always in
  main code

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Packages

• Instead of declaring all components can declare
  all components in a PACKAGE, and INCLUDE the
  package once
• This makes the top-level entity code cleaner
• It also allows that complete package to be used
  by another designer
• A package can contain
• Components
• Functions, Procedures
• Types, Constants

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Package example (1)

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• PACKAGE GatesPkg IS
• COMPONENT mux2to1
• PORT (w0, w1, s IN STD_LOGIC
• f OUT STD_LOGIC )
• END COMPONENT
• COMPONENT priority
• PORT (w IN STD_LOGIC_VECTOR(3 DOWNTO 0)
• y OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
• z OUT STD_LOGIC )
• END COMPONENT

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Package example (2)

• COMPONENT dec2to4
• PORT (w IN STD_LOGIC_VECTOR(1 DOWNTO 0)
• En IN STD_LOGIC
• y OUT STD_LOGIC_VECTOR(0 TO 3) )
• END COMPONENT
• COMPONENT regn
• GENERIC ( N INTEGER 8 )
• PORT ( D IN STD_LOGIC_VECTOR(N-1 DOWNTO
  0)
• Enable, Clock IN STD_LOGIC
• Q OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) )
  
• END COMPONENT

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Package example (3)
constant ADDAB std_logic_vector(3 downto 0)
"0000" constant ADDAM std_logic_vector(3
downto 0) "0001" constant SUBAB
std_logic_vector(3 downto 0) "0010" constant
SUBAM std_logic_vector(3 downto 0)
"0011" constant NOTA std_logic_vector(3 downto
0) "0100" constant NOTB std_logic_vector(3
downto 0) "0101" constant NOTM
std_logic_vector(3 downto 0) "0110" constant
ANDAB std_logic_vector(3 downto 0)
"0111" END GatesPkg
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Package usage (1)

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• USE work.GatesPkg.all
• ENTITY priority_resolver1 IS
• PORT (r IN STD_LOGIC_VECTOR(5 DOWNTO 0)
• s IN STD_LOGIC_VECTOR(1 DOWNTO 0)
• clk IN
  STD_LOGIC
• en IN STD_LOGIC
• t OUT STD_LOGIC_VECTOR(3 DOWNTO 0) )
• END priority_resolver1
• ARCHITECTURE structural OF priority_resolver1 IS
• SIGNAL p STD_LOGIC_VECTOR (3 DOWNTO 0)
• SIGNAL q STD_LOGIC_VECTOR (1 DOWNTO 0)
• SIGNAL z STD_LOGIC_VECTOR (3 DOWNTO 0)
• SIGNAL ena STD_LOGIC

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Package usage (2)

• BEGIN
• u1 mux2to1 PORT MAP ( w0 gt r(0) ,
• w1 gt r(1),
• s gt s(0),
• f gt p(0))
• p(1) lt r(2)
• p(2) lt r(3)
• u2 mux2to1 PORT MAP ( w0 gt r(4) ,
• w1 gt r(5),
• s gt s(1),
• f gt p(3))
• u3 priority PORT MAP ( w gt p,
• y gt q,
• z gt ena)
• u4 dec2to4 PORT MAP ( w gt q,
• En gt ena,

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Aldec Compilation Order

• Include package before top-level

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Mixing Design Styles Inside of an Architecture
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VHDL Design Styles
VHDL Design Styles
structural
behavioral
Components and interconnects
Concurrent statements
Sequential statements

• Registers
• Shift registers
• Counters
• State machines

synthesizable
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Mixed Style Modeling

• architecture ARCHITECTURE_NAME of ENTITY_NAME is
• Here you can declare signals, constants,
  functions, procedures
• Component declarations
• No variable declarations !!
• begin
• Concurrent statements
• Concurrent simple signal assignment
• Conditional signal assignment
• Selected signal assignment
• Generate statement
• Component instantiation statement
• Process statement
• inside process you can use only sequential
  statements
• end ARCHITECTURE_NAME

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PRNG Example (1)

• library IEEE
• use IEEE.STD_LOGIC_1164.all
• use work.prng_pkg.all
• ENTITY PRNG IS
• PORT( Coeff in std_logic_vector(4
  downto 0)
• Load_Coeff in std_logic
• Seed in std_logic_vector(4
  downto 0)
• Init_Run in std_logic
• Clk in std_logic
• Current_State out std_logic_vector(4
  downto 0))
• END PRNG
• ARCHITECTURE mixed OF PRNG is
• signal Ands std_logic_vector(4 downto
  0)
• signal Sin std_logic
• signal Coeff_Q std_logic_vector(4 downto
  0)
• signal Shift5_Q std_logic_vector(4 downto
  0)

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PRNG Example (2)

• -- Data Flow
• G FOR I IN 0 TO 4 GENERATE
• Ands(I) lt Coeff_Q(I) AND Shift5_Q(I)
• END GENERATE
• Sin lt Ands(0) XOR Ands(1) XOR Ands(2) XOR
  Ands(3) XOR Ands(4)
• Current_State lt Shift5_Q
• -- Behavioral
• Coeff_Reg PROCESS(Clk)
• BEGIN
• IF Clk'EVENT and Clk '1' THEN
• IF Load_Coeff '1' THEN
• Coeff_Q lt Coeff
• END IF
• END IF
• END PROCESS
• -- Structural
• Shift5_Reg Shift5 PORT MAP ( D gt Seed,

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Synthesis
57
Resources Required Reading
Movie Demos
Integrated Interfaces Active-HDL with
Synplify Integrated Synthesis and Implementation
Active-HDL Help
58
Design flow (1)
Design and implement a simple unit permitting to
speed up encryption with RC5-similar cipher with
fixed key set on 8031 microcontroller. Unlike in
the experiment 5, this time your unit has to be
able to perform an encryption algorithm by
itself, executing 32 rounds..
Specification (Lab Experiments)
VHDL description (Your Source Files)
Library IEEE use ieee.std_logic_1164.all use
ieee.std_logic_unsigned.all entity RC5_core is
port( clock, reset,
encr_decr in std_logic
data_input in std_logic_vector(31 downto 0)
data_output out std_logic_vector(31
downto 0) out_full in
std_logic key_input in
std_logic_vector(31 downto 0)
key_read out std_logic ) end
AES_core
Functional simulation
Synthesis
Post-synthesis simulation
59
Synthesis Tools
Xilinx XST
Synplify Pro

• and others

60
Logic Synthesis
VHDL description
Circuit netlist
architecture MLU_DATAFLOW of MLU is signal
A1STD_LOGIC signal B1STD_LOGIC signal
Y1STD_LOGIC signal MUX_0, MUX_1, MUX_2, MUX_3
STD_LOGIC begin A1ltA when (NEG_A'0')
else not A B1ltB when (NEG_B'0') else not
B YltY1 when (NEG_Y'0') else not
Y1 MUX_0ltA1 and B1 MUX_1ltA1 or
B1 MUX_2ltA1 xor B1 MUX_3ltA1 xnor
B1 with (L1 L0) select Y1ltMUX_0 when
"00", MUX_1 when "01", MUX_2 when
"10", MUX_3 when others end MLU_DATAFLOW
61
Features of synthesis tools

• Interpret RTL code
• Produce synthesized circuit netlist in a standard
  EDIF format
• Give preliminary performance estimates
• Display circuit schematic corresponding to EDIF
  netlist

62
Timing report after synthesis

• Performance Summary
• Worst slack in design -0.924
• Requested Estimated
  Requested Estimated
• Starting Clock Frequency Frequency
  Period Period Slack
• --------------------------------------------------
  --------------------------------------------------
  ---
• System 85.0 MHz 86.4 MHz
  11.765 11.572 0.193
• 
  

Slack Estimated Clock Period Requested Clock
Period
Negative Slack means timing violations Positive
Slack means positive margin before timing
violation