Title: Test and Evaluation of HAL25 The ALICE SSD Front-End Chip
1Test and Evaluation of HAL25 The ALICE SSD
Front-End Chip
C. Hu-Guo, D. Bonnet, J.P. Coffin, G. Deptuch, C.
Gojak, J.R. Lutz, I. Valin IReS (IN2P3-ULP),
Strasbourg, France J.D. Berst, G. Claus, C.
Colledani LEPSI (IN2P3-ULP), Strasbourg, France
2HAL25 History
- 1st generation chip ALICE128C (1997)
- Designed on a CMOS 1.2 mm process
- Good performance up to 50 Krad of the ionising
dose - Used for the SSD front-end of the STAR tracker
- HAL25
- Designed on a deep submicron 0.25 mm process
- For safety margins in radiation environment
- Version 1 (MPW4-March-2001)
- Version 2 (MPW6-November-2001)
3HAL25 Block Diagram
- - 128 Analogue Channels
- Preamplifier
- Shaper
- Storage capacitor
- - Analogue Multiplexer
- Differential Current Output
- 128 Test Pulse Generators
JTAG remote control
- Set Bias Generator
- Set Transparent Mode
- Set Test Pulse Generator
- Perform Boundary Scan
4Design Features in HAL25
- Single power supply 0-2.5 V
- ? 14 MIP dynamic range front-end amplifier
- Differential current output
- Registers with majority vote logic
- Prevent Single Event Upset (SEU)
- Adjustable internal current source (?15)
- Compensate process variation
5Front-end Amplifier
- Shaper feedback resistor ? source degenerated
differential pair - No switchinverter circuitry
- Vout Vdc (DC level)
- Maximum dynamic range (? 14 MIP ) for GV 50
mV/MIP - Linearity lt 4
- Tuneable transconductance
- Tuneable peaking time 1.4ms lt t lt 2.2 ms
6HAL25 Layout
- Chip dimension 3.65 x 11.90 mm2
- TAB compatible I/O pads
- Size pitche
- ESD protected I/O Pads
- CMOS for slow control
- LVDS for readout
7Pedestal Distribution
- For 1 chip (128 channels )
- ?I ? 34 mA
- 1 MIP signal
- After pedestal subtraction
8Gain linearity
Current!
- Agree with simulation
- Measured pulse fit ideal CRRC curve
- GI 200-250 ?A / MIP (22000 e-)
- Dynamic range 14 MIP
- Linearity lt 2.5 ( 10 MIP) Linearity
lt 4 ( 14 MIP)
9Output Pulse Uniformity (MPW6 run)
- With the internal test pulse generator ? 8 MIP
signal - 62 chips x 128 ch (on 2 wafers)
- Average output pulse amplitude ? 1875 mA
- ? ? 63 mA ?Good uniformity
10Noise
- Noise distribution (128 ch)
- ENC _at_ 0pF 215 e-
- s 5 e-
- ENC 215 25 e-/pF
- For peaking time 1.4 ms
11Maximum readout frequency
- Nominal readout frequency 10 MHz
- Readout up to 20 MHz with degradation of
- Linearity Gain
12New Request for High Input Rate
- Pile-up depends on
- Input signal time intervals
- Input signal amplitudes
- Decay times
- Preamplifier decay time
- Nominal a few ms (? hundreds Hz)
- Can be decreased by changing VPRE ? Rf f(VPRE)
- Noise increased
- Gain reduced
- Shaper decay time
- ? 8peaking time (? few tens KHz)
- Ref. Pile-up phenomena in HAL25
ftp//lepsi.in2p3.fr/pub/HAL25/Pile_up.pdf
13Yield
- 340 circuits tested from 2 MPW
- ? 50 OK
- Problem seems to be related to
- 128 channels architecture for deep sub-micron
process - Long lines for common biases and slow signals
- No errors detected by Design Rule Checkers
- 0.25mm community investigates the problem
- New version of HAL25
- intended to understand yield issue
14Conclusion
- HAL25 meets specifications
- Irradiation test with X-ray up to 500 Krad
- No performance degradation
- Version 3 (MPW8 September 2002)
- Focused on yield improvement
- ESD I/O Pads
- Low power LVDS Pads
- Fuse programmable chip serial number (24 bit)
- Future work
- Test ? HAL25 Detector