Layout Considerations of Non-Isolated Switching Mode Power Supply

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Layout Considerations of Non-Isolated Switching
Mode Power Supply
Presented by Henry Zhang Power Business
Unit Linear Technology Corp. Oct. 2003
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1. General Discussion
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Plan of the Power Supply Layout

• In the system, power supply should be close to
• its load devices.
• Cooling fan should be close to the supply to
  limit
• its component thermal stress.
• Select the right number of layers and copper
  thickness
• The large size passive components (inductors,
  bulk
• capacitors) should not block air flow to power
  MOSFETs

• Power supply designer should always works
  closely with
• PCB designer on the critical layout design

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4-Layer PCB Layer Placement
Undesired
Layer 1 Power Component
Layer 2 Small Signal
Layer 3 GND
Layer 4 Small signal / controller
Power
Signal
GND
PCB capacitance
High current loop Pulsating current loop
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6-Layer PCB - Layer Placement
Undesired
Desired
Layer 1 Power Component
Layer 1 Power Component
Layer 2 Small signal
Layer 2 GND plane
Layer 3 GND plane
Layer 3 Small Signal
Layer 4 DC Voltage or GND plane
Layer 4 Small Signal
Layer 5 Small signal
Layer 5 DC Voltage or GND plane
Layer 6 Power Component / Controller
Layer 6 Power Component / Controller

• DC power and ground planes function as AC
  reference planes.
• As a general rule, the reference planes of a
  multi-layer PCB design should not be segmented.

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Small Signal Traces on Reference Layer

• If the small signal traces have to be routed on
  the reference layer, use short traces with proper
  direction

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Copper Thickness and PCB Resistance
Copper resistivity (?/cm)
T Copper temperature in oC
Resistance of copper
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2. DC/DC Converter Power Stage Layout
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Buck Converter Current Paths
Continuous Current
Pulsating Current

• Identify the continuous and pulsating current
  paths
• Pay special attention to pulsating current paths
  and high
• dv/dt switching node

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Parasitic Inductance in the Current Pathsand
Example Layout (Buck)

• Minimize loop between HF capacitor and MOSFETs
• It is desirable to keep CHF, top FET and bottom
  FET on the same layer
• Use multiple vias for power connection

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Boost Converter Current Paths
Continue Current
High dv/dt node
Pulsating Current
LF
D
SW
Vo
Vo
VIN
CHF
CIN
Co
SB
Load
PGND

• Minimize the critical pulsating current loop on
  the output side

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Output Noise Decoupling Capacitor (Boost)

• Minimize the critical pulsating current loop on
  the output side

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12V-to-2.5V/30A LTC3729 Supply Layout Example
VIN (12V)
VO (2.5V)
LF1
QT
CIN
SW1
LTC3729
Co
QB
GND
GND
Co
SW2
VIN
VO (2.5V)
(a)
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Noise Problem _at_ Heavy Load
Io 0A
Io gt 13.3 A
vSW1
iLF1
vSW2
(c)
(b)
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Input Ceramic Capacitors Make a Difference
(a)
Io 0A
vSW1
iLF1
vSW2
(b)
(c)
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Land Patterns of Power Components
Undesired
Connected Via
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3.3V/40A LTC3729 Layout Design Example
High Current Trace
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Examples of a 2-Phase DC/DC Power Stage
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Separation of Input Paths Among Supplies
Undesired
Desired
RPCB1
RPCB
DC/DC 1
Cin
Cin
RPCB2
DC/DC 1
DC/DC 2
PGND
PGND
PGND
DC/DC 2
PGND
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3. Layout of the Controller and MOSFET Drivers
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Decoupling Capacitor and Separated Grounds
LTC3729
RUN/SS
TG1
SEN1
R
RSENSE
C
SW1
SEN1-
R
C
EAIN
SGND Island
BG1
INTVCC
ITH
C
C
PGND
SGND
BG2
VDIFF
PGND Plane
SW2
SEN2-
R
TG2
RSENSE
C
SEN2
R
Shortest Distance
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Signal Ground and Power Ground

• Components connected to following pins use SGND

- EAIN, RUN/SS, ITH, UVADJ, PHAMD, PLLIN, PLLFTR,
FCB, CLKOUT

• Components connected to following pins use PGND

- BOOST, 5V, PGND

• The SGND and PGND can be tied together underneath
  the IC.

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QFN Package Controller Layout

• Exposed SGND pad must be soldered to PCB
• Use multiple vias to connect SGND pad to both
  SGND and PGND layers
• PGND pin also connects to SGND pad underneath
  the IC

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Gate Driver Traces
LTC3729
Route together
QT
BOOST1
TG1
SW1
INTVCC
BG1
QB
C
PGND
Automatically coupled AC ground return current
PGND Plane
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IC Signal Trace Width
Following are the trace width values we use in
Polyphase demo board
20 mils TG, BG, SW
25 mils - 5V, Vcc, PGND
15 mils Current sensing, feedback, ITH, etc.
10 mils Short traces that directly connected to
IC pads
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Current Sensing Traces
RSENSE
LF
Vo
Direct trace connection. Do NOT use via.
LTC3729
This via should NOT touch any other internal
Vo copper plane.
SENSE-
R
C
SENSE
R

• Kevin sensing of the current signal
• Keep current sensing traces away from noisy
  traces / copper area or use ground layer for
  shielding.

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Sensitive Traces and Noisy Traces

• Most sensitive traces

• Current sensing (SENSE/-), EAIN, ITH, SGND
• Sense / - traces for each channel should be
  routed together
• With minimum trace spacing. The filter capacitor
  should be as close to
• IC pins as possible. The filter resistor should
  be close to filter capacitor.
• Keep sensitive traces away from noisy traces.

• Sensitive traces

Vos/-, DIFFOUT, PLLFTR, CLKOUT

• CLKOUT is a sensitive trace but it is also a
  noisy trace. So keep it away from
• other small signal sensitive traces.

• Most noisy traces

SW, TG, BOOST, BG

• Keep them away from sensitive traces.
• Avoid overlapping between large SW copper area
  and sensitive traces in two
• neighborhood layers.
• - For each channel, route the SW and TG trace
  together with minimum space.

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Summary - Layout Checklist

• Plan of the layout

• Location of the supply / load / bulk capacitors
• of layers / layer placement / copper thickness

• Power stage layout

• Power component placement
• Power component land patterns
• Identify pulsating current paths
• Decouple capacitor close to MOSFET
• Short / wide copper trace and multiple vias for
  high current

• Controller circuit layout

• Decoupling capacitors close to pins
• Separate signal / power grounds
• Current sensing
• De-couple sensitive and noisy traces
• Gate driver traces
• Select proper trace width