Design and Implementation of AllDigital FastLocked DLLBased Clock Generators

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????????????????????????????? Design and
Implementation of All-DigitalFast-Locked
DLL-Based Clock Generators
Advisor Shen-Iuan Liu Student Chuan_kang Liang

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Motivations

• For a clock generator, why DLL?
• Unconditional stability first order system
• No jitter accumulation from the delay line
• Why all digital?
• Robust and insensitive to PVT variation
• Easily to port to advanced process
• Fast lock SAR algorithm
• The limitations of the DLL
• False lock and harmonic lock
• Trade-offs between the operating frequency and
  operation range
• No frequency synthesis

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An Ultra Wide-Range Delay-Locked-Loop with Cyclic
Technique

• Methods
• New lock algorithm
• New duty-cycle correction concept
• Modified SAR algorithm to achieve fast locked and
  closed loop tracking ability
• Features
• All digital DLL
• Wide range 1520MHz
• Fast locked 16 input clock
• DCC with single reference
• Closed loop after locked
• High extension enlarge range with the same lock
  time
• Small area 0.2mm x0.3mm active area
• Low power smaller than 15mw_at_500MHz

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An All-Digital Fast-Locked DLL-Based Frequency
Synthesizer

• Methods
• New selection concept and PFD to eliminate the
  initial constraint.
• Modified SAR algorithm to achieve fast lock and
  closed loop tracking ability.
• Features
• The first one all-digital DLL-based frequency
  synthesizer
• Multiplication ratio is programmable
• Closed loop -- deal with environment variation
• No initial frequency constraint
• Small area 0.216mm2 active area
• Low power 17mw_at_450MHz