20 GHz LC Tank VCO Design with Onchip Inductor

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20 GHz LC Tank VCO Design with On-chip
Inductor/ Transmission Line Modeling Adnan
Seferagic and Ramana Malladi
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Outline

• VCOs in Wireless Transceivers and PLLs
• Different components of a VCO
• Varactor and Inductor design and Modeling
• Limitations with Lumped element Inductors
• CMOS vs Bipolar
• Simple Cross-coupled VCO and Its Limitations
• Possible VCO Designs for High-frequencies
• Conclusions

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Other Applications of High-Frequency VCOs

• Demands for ever-increasing frequency and
  bandwidth of data communications

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Challenges with High-Frequency Wireless Designs

• We need High-speed Transistor Technology
• We need High-Q inductors and Varactors
• Designs require Larger Chip area
• Very sensitive to Parasitics

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Varactors

• Varactor Bias-dependent capacitor
• PN-diodes, Schottky, MOS Caps can be used as
  Varactors
• Junction Cap Variation is given by
• Varactor should have
• High Tunability (3 or greater )
• Quality Factor, Q, must be high (20 or greater)
• Device must exhibit linearity

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Simple Inductors
Groves et.al., WCM-2007
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Transmission Lines as Inductors
The impedance anywhere along a terminated T.Line
is
Z0
ZL
l
If the transmission line is lossless, a0
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Transmission Lines as Inductors and Capacitors
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Bipolar Vs CMOS Designs

• FETs
• gm for FETs is one decade smaller than Bipolars
• gm, Vth uncertainties
• Lossy Substrate
• Higher 1/f noise
• Higher thermal noise
• Bipolars
• Very high-speeds are achievable even at lower
  nodes
• Can utilize high-resistivity substrates gtbetter
  Q inductors
• Very low 1/f noise gt lower phase-noise for
  VCOs
• Very low high-frequency Noise figure

For this project we will be using CMOS. This
presentation mixes both technologies
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Limitations with Cross-Coupled Topology at High
Frequencies

• The losses of the LC tank are represented by Rt
• The ve Resistance Rp is needed to compensate
  the losses
• Rp-2/gm at low frequencies. Rp is ve upto a
  maximum frequency fcross
• fV is input bandwidth of the npn (mainly from
  the Rb and Cbe and Cbc)
• (bandwidth from the collector when applying a
  voltage source between Base and Grounded Emitter)
• fcross 25GHz in a 70GHz technology

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Cascaded Emitter Followers With Resistive Load
Topology
Veenstra et.al., ISSCC 2004

• A ve Resistance implemented using a cascaded
  ckt of 2 EFs, with Resistive Output Load (RL)
• RL of output EF (T2) translates into a
  capacitive load for input EF T1 and
• the capacitive load of EF-T1 translates into a
  ve resistance at the base of T1
• The maximum attainable oscillation frequency for
  this topology is flimit (gtfcross)

CLTotal capacitance at the output of the EF-T1
(Cin-T2Cbc..)
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General Design Approaches
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Push-Push Oscillator Operation

• Requires the Transistors operate in only the
  odd-mode
• This is assured by proper choice of Terminating
• impedance and Gain at fundamental
• Oscillation condition -Rq gt Rs
• Frequency of Oscillation -Xq(XL-XV)0
• The transistors oscillate out-of phase with each
  other,
• causing f0 to cancel out and 2nd. Harm. to add
  in phase
• To eliminate the possibility of oscillation in
  even-mode,
• -Rq lt Rs 2.RL
• In Summary, Rs lt -Rq lt Rs2.RL
• These conditions are easy to meet

Smith , MTT-S Digest , 1989 (725-728) Kobayashi,
JSSC, 1999 (1225-32)
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Schematic of a D-Band CMOS VCO

• M1 and M2 with Lg, Cs provide ve resistance
• Ld and Cvar form the LC-tank resonator
• Ls Cs (source resonator) provides ve R at
  freq. where
• CMOS does not have enough gm to provide ve R

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Conclusions and Directions for Future Work

• Several choices of VCO Topology exist for 20 GHz
  Designs in CMOS
• We will make choice based on whether the designs
  are in 0.13 um or 0.25 um
• and the specs we are designing to.
• Transmission Lines (CPW or Microstrip depending
  on kit) will be used for the Tank

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