Designing Logic Circuits for Probabilistic Computation in the Presence of Noise

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Designing Logic Circuits for Probabilistic
Computation inthe Presence of Noise

• Kundan Nepal
• Iris Bahar
• Joseph Mundy
• William R. Patterson
• Alexander Zaslavsky
• Brown University
• Division of Engineering
• Providence, RI 02912

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Motivation

• Current computer architecture approaches are
  reaching their practical limits.

Nanotechnology research
Si Based devices
Exotic Non-Si alternative devices
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Characteristics of nanodevices

• Devices will have high failure rates
• Manufacturing defects
• Time varying dynamic faults
• Energy difference between logicstates will
  approach the thermal limit
• computation will become probabilistic reflecting
  uncertainty in thermodynamics

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Current Nanoarchitecture Approaches

• Test and route around failures
• Use redundant logic for error correction
• Neural Networks

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Our Approach

• Inspired by ideas from von Neumannand neural
  networks
• Based on Markov random fields
• Dynamically defect tolerant
• Adapts to errors as a natural consequenceof
  probability maximization
• Removes need to actually detect faults

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Contributions of our work

• We propose the first technologically realistic
  CMOS implementation of a new logic style based on
  the Markov random field (MRF) probabilistic
  paradigm.
• We consider various forms of noise and evaluate
  their impact on circuit reliability.
• Using benchmark circuits we show that MRF
  elements have superior tolerance to soft errors.

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Why Markov Random Fields?

• MRF can express arbitrary computation.
• Its operation does not depend on perfect devices
  or perfect connections.
• Logic operation is naturally achieved through
  probabilistic computation.
• MRF has been widely used in pattern recognition
  and communication

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Markov Random Fields

• Probability of variable being in a certain state
  depends on state of neighboring connections
  (associated cliques).
• Maximize probability of correct operation by
  minimizing

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Circuits to MRF
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Gibbs model for an Inverter
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Physical Realization of MRF

• Possible candidates
• Tunneling-based devices (faster)
• Carbon nanotubes (excellent current carriers)
• Molecular transistors (area efficient)
• Magnetic spins (direct mapping of Gibbsenergy
  model)
• Our choice
• Ultimate CMOS transistors.

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Ultimate CMOS logic

• Plagued by noise due to
• Thermal noise
• Threshold variations (noise margin reduction)
• Coupling
• Power/Gnd bounce
• The sources of signal noise in ultimate
  transistors are a subject of current research.
• We use a Gaussian distributed noise model.

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Mapping MRF to CMOS

• Each logic state, xi, should be represented as a
  bistable element, taking on logical values of 0
  and 1. The probability for any other signal
  value should be low.
• The constraints of each logic graph clique should
  be enforced by feedback to the appropriate
  elements, implementing the logic compatibility
  functions to factorize and maximize the joint
  probability of the correct logical values.

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CMOS mapping of MRF Inverter
M
1
1
1
0
0
0
0
0
1
1
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Simulation Setup

• Simulation Tool Silvaco SmartSPICE
• Model 70nm Berkeley PredictiveTechnology Model.
• Supply Voltage 0.15 V
• Threshold Voltage
• NMOS 0.2V
• PMOS -0.22V
• Temperature 100ºC
• Noise Model Gaussian Noise
• Mean 0V
• Standard Deviation 60mV RMS

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CMOS mapping of MRF Inverter
Vin
Vcmos
Vmrf
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Noise Immunity MRF vs. DCVS
Vin
Vdcvs
Vmrf
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CMOS mapping MRF NAND
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MRF NAND Noise Immunity
Vin1
Vin2
Vcmos
Vmrf
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Threshold Variations

• Immunity of MRF inverter to threshold variation
• VTH0.2V (NMOS) -0.22V (PMOS).
• ?VTH20mV

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Kullback-Leibler distance Quantifying noise
immunity
measure of the discrepancy between the actual
output signal probability Preal of a logical
element or circuit and the ideal (correct) output
Pideal the smaller the KLD, the better the noise
immunity of the circuit
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Kullback-Leibler distance Quantifying noise
immunity

• MRF has a KLD closest to 0. (i.e. it is the one
  with the least noise and closest to the ideal
  distribution)

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Larger circuits Noise immunity

• Noise immunity comparison using KLD for some
  small MCNC91 benchmark circuits. MRF circuits are
  always better.

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Conclusions

• Created CMOS mapping of devices using the MRF
  based probabilistic computation framework
• Considered various forms of noise and their
  impact on reliability
• Thermal noise
• Threshold variation
• Showed through SPICE simulations that MRF
  elements have excellent noise and dynamic fault
  immunity

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Future Work

• Investigate how this approach can be extended to
  more complex logic
• Design sequential elements based on MRF principle
• Integrate dynamic errors and permanent defects
  for complete analysis

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• This work was supported by a grant from the
  National Science Foundation.

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THANK YOU
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Noise distribuiton symmetry