SVX4 Status

1
SVX4 Status
2
Testing

• Testing is never completed! You will always be
  going back to investigate problems.
• What remains to be done?
• ESD testing (to be done today)
• There is a D0 note in progress that explains all
  the test results and modifications to date.

3
Modification List

• What has been found? (completed items checked)
• 1) choose SVX4 Version 2 as the basic design
• 2) add pullup or pulldown on D0Mode (this is now
  a pulldown)
• 3) add pullup on USESEU
• 4) pullup bit7 of chipid
• 5) pulldown bit 67 of cellid
• 6) hardwire PRIOUT driver strength bits
• 7) change ADC control signal latching scheme to
  (not(readout))
• 8) add 2 bits to SR
• 9) add VCAL switch
• 10) add on-chip decoupling caps to BIAS
• 11) layout/design change for ADC pedestal
  variation
• 12) pipeline cell pedestal variation
• 13) ADC comparator design
• 14) Receiver

4
Strategy

• We are planning a 2-version submission
• Version 4.2aminimum changes, back-up solution
• 2) add pullup or pulldown on D0Mode
• 3) add pullup on USESEU
• 4) pullup bit7 of chipid
• 5) pulldown bit 67 of cellid
• 6) hardwire PRIOUT driver strength bits
• 7) change ADC control signal latching scheme to
  not(readout)
• 8) add 2 bits to SR
• 9) add VCAL switch
• 11) ADC comparator design LEVEL ILBL changes in
  bias circuit, comprst driver
• 15) Receiver
• Version 4.2bbetter performance, planned
  pre-production chip
• Same as 4.2a, but
• 12) pipe cell pedestal variationwiden metal
  lines
• 10) add on-chip decoupling caps to BIAS
• 13) ADC comparator design LEVEL IIFNAL changes
  in bias, output stage, input caps, local comprst
  buffer, for better performance

5
4-1-1

• For your information
• The retical used for making chips has six copies
  on it
• We are planning the following breakdown
• 4 from the maximal or aggressive design
• 1 from the minimal design
• 1 from the original design (to be used as a
  baseline)

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Schedule

• 4.2a
• Backend digital done this week
• ADC bow study Nov 13-20
• Front end and LBL ADC changes done by Nov 27th
• 4.2b
• Insert FNAL ADC Nov 27th
• Insert BIAS caps and pipeline metal Nov 27th
• Both versions
• Incorporate receiver fix Dec 2nd
• Full chip simulation and ADC Monte-Carlo
  simulation starts Dec 2nd
• 1-month verification starts Dec 12th, on-schedule