ECE 545Digital System Design with VHDL Lecture 12

1
ECE 545Digital System Design with VHDLLecture 12

• Advanced VHDL Syntax,VHDL Modeling of
  Microprocessors
• 11/25/08

2
Outline

• Advanced VHDL Syntax
• Arrays
• Subprograms
• Functions
• Procedures
• Operators, Types, Configuration
• VHDL Modeling of Microprocessors
• Single purpose processors versus general purpose
  processors
• Microcontroller architecture overview
• Simple Microcontroller design
• Fibonacci sequence on Simple Microcontroller

3
Resources

• Volnei Pedroni, Circuit Design with VHDL
• Chapter 3, Data Types
• Chapter 4, Operators and Attributes
• Chapter 11, Functions and Procedures
• Vahid and Givargis, Embedded System Design A
  Unified Hardware/Software Introduction
• Chapter 3, General Purpose Processors Software

4
Constrained Array Types
5
Constrained versus Unconstrained Arrays

• Constrained array types have fixed beginning and
  end values
• Unconstrained array types have non-determined
  beginning and end values
• Can only create subtypes arrays from
  unconstrained arrays

6
One-dimensional arrays Examples (1)

• type word_asc is array(0 to 31) of std_logic
• type word_desc is array(31 downto 0) of
  std_logic
• ..
• signal buffer_register word_desc
• ..
• buffer_register(6) lt '1'
• ..
• variable tmp word_asc
• ..
• tmp(5) '0'

7
One-dimensional arrays Examples (2)

• type controller_state is (initial, idle, active,
  error)
• type state_counts_imp is array(idle to error) of
  natural
• type state_counts_exp is array(controller_state
  range idle to error) of natural
• type state_counts_full is array(controller_state)
  of natural
• ..
• variable counters state_counts_exp
• ..
• counters(active) 0
• ..
• counters(active) counters(active) 1

8
Unconstrained Array Types
9
Predefined Unconstrained Array Types

• Predefined
• bit_vector array of bits
• string array of characters
• Defined in the ieee.std_logic_1164 package
• std_logic_vector array of std_logic_vectors

10
Predefined Unconstrained Array Types

• subtype byte is bit_vector(7 downto 0)
• . . .
• variable channel_busy bit_vector(1 to 4)
• . . .
• constant ready_message string ready
• . . .
• signal memory_bus std_logic_vector (31 downto 0)

11
User-defined Unconstrained Array Types

• type sample is array (natural range ltgt) of
  integer
• . . .
• variable long_sample sample(0 to 255)
• . . .
• constant look_up_table_1 sample (127, -45,
  63, 23, 76)

12
Attributes of Arrays and Array Types
13
Array Attributes

• Aleft(N) left bound of index range of
  dimension N of A
• Aright(N) right bound of index range of
  dimension N of A
• Alow(N) lower bound of index range of dimension
  N of A
• Ahigh(N) upper bound of index range of
  dimension N of A
• Arange(N) index range of dimension N of A
• Areverse_range(N) reversed index range of
  dimension N of A
• Alength(N) length of index range of dimension N
  of A
• Aascending(N) true if index range of dimension
  N of A
• is an ascending range,
  false otherwise

N only required when the array is more than one
dimension
14
Array Attributes - Examples

• type A is array (1 to 4, 31 downto 0)
• Aleft(1) 1
• Aright(2) 0
• Alow(1) 1
• Ahigh(2) 31
• Arange(1) 1 to 4
• Alength(2) 32
• Aascending(2) false

15
Subprograms
16
Subprograms

• Include
• functions and procedures
• Commonly used pieces of code
• Can be placed in a library, and then reused and
  shared among various projects
• Abstract operations that are repeatedly performed
• Type conversions
• Use only sequential statements, the same as
  processes

17
Typical locations of subprograms
PACKAGE PACKAGE BODY
LIBRARY
global
ENTITY
FUNCTION / PROCEDURE
local for all architectures of a given entity
ARCHITECTURE Declarative part
local for a given architecture
18
Functions
19
Functions basic features

• Functions
• always return a single value as a result
• Are called using formal and actual parameters the
  same way as components
• never modify parameters passed to them
• parameters can only be constants (including
  generics) and signals (including ports)
• variables are not allowed the default is a
  CONSTANT
• when passing parameters, no range specification
  should be included (for example no RANGE for
  INTEGERS, or TO/DOWNTO for STD_LOGIC_VECTOR)
• are always used in some expression, and not
  called on their own

20
Function syntax

• FUNCTION function_name (ltparameter_listgt)
• RETURN data_type IS
• declarations
• BEGIN
• (sequential statements)
• END function_name

21
Function parameters - example

• FUNCTION f1
• (a, b INTEGER SIGNAL c STD_LOGIC_VECTOR)
• RETURN BOOLEAN IS
• BEGIN
• (sequential statements)
• END f1

22
Function calls - examples

• x lt conv_integer(a)
• IF x gt maximum(a, b) THEN ....
• WHILE minimum(a, b) LOOP
• .......

NOTICE Functions are not stand-alone statements!
23
Functions Examples

• Example 1 Log2Ceil function in package
• Example 2 Power function in architecture
• Example 3 Power function in package
• Example 4 Type conversion function in package

24
Example 1 Log2Ceil functionPackage

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• PACKAGE my_package IS
• FUNCTION log2_ceil (CONSTANT s INTEGER) RETURN
  INTEGER
• END my_package
• PACKAGE body my_package IS
• FUNCTION log2_ceil (CONSTANT s INTEGER)
  RETURN INTEGER IS
• VARIABLE m,n INTEGER
• BEGIN
• m 0
• n 1
• WHILE (n lt s) LOOP
• m m 1
• n n2
• END LOOP
• RETURN m
• END log2_ceil

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Example 1 Log2Ceil functionfunction call

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• USE ieee.std_logic_unsigned.all
• USE ieee.std_logic_arith.all
• USE work.my_package.all
• ENTITY log2_int IS -- multiplies x by
  log2_ceil(m) to produce y
• GENERIC (m INTEGER 20)
• PORT (x IN STD_LOGIC_VECTOR(3 DOWNTO 0)
• y OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
• )
• END log2_int
• ARCHITECTURE log2_int OF log2_int IS
• CONSTANT l2m INTEGER log2_ceil (m)
• SIGNAL r STD_LOGIC_VECTOR(3 DOWNTO 0)
• BEGIN
• r lt std_logic_vector(conv_unsigned(l2m,4)
  )
• y lt xr

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Example 2 Power function in architecture

• library IEEE
• use IEEE.std_logic_1164.all
• use IEEE.std_logic_unsigned.all
• ENTITY powerOfFour IS
• PORT(
• X IN STD_LOGIC_VECTOR(3 downto 0)
• Y OUT STD_LOGIC_VECTOR(7 downto 0)
• )
• END powerOfFour

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Example 2 Power function in architecture cont'd

• ARCHITECTURE behavioral OF powerOfFour IS
• FUNCTION Pow ( SIGNAL NINTEGER Exp INTEGER)
• RETURN INTEGER IS
• VARIABLE Result INTEGER 1
• BEGIN
• FOR i IN 1 TO Exp LOOP
• Result Result N
• END LOOP
• RETURN( Result )
• END Pow
• SIGNAL Xint,Yint INTEGER
• BEGIN
• Xint lt conv_integer(unsigned(X))
• Yint lt Pow(Xint,4)
• Y lt std_logic_vector(conv_unsigned(Yint,7))

28
Example 3 Power function in package

• LIBRARY IEEE
• USE IEEE.std_logic_1164.all
• PACKAGE specialFunctions IS
• FUNCTION Pow( SIGNAL N INTEGER Exp
  INTEGER) RETURN INTEGER
• END specialFunctions
• PACKAGE BODY specialFunctions IS
• FUNCTION Pow(SIGNAL N INTEGER Exp INTEGER)
• RETURN INTEGER IS
• VARIABLE Result INTEGER 1
• BEGIN
• FOR i IN 1 TO Exp LOOP
• Result Result N
• END LOOP
• RETURN( Result )
• END Pow
• END specialFunctions

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Example 4 Type conversion functionpackage

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• PACKAGE my_package IS
• FUNCTION conv_integer (SIGNAL vector
  STD_LOGIC_VECTOR)
• RETURN INTEGER
• END my_package
• PACKAGE BODY my_package IS
• FUNCTION conv_integer (SIGNAL vector
  STD_LOGIC_VECTOR)
• RETURN INTEGER IS
• VARIABLE result INTEGER RANGE 0 TO
  2vector'LENGTH - 1
• VARIABLE carry STD_LOGIC
• BEGIN
• IF(vector(vector'HIGH))'1' THEN result1
• ELSE result 0
• FOR i IN (vector'HIGH-1) DOWNTO
  (vector'LOW) LOOP
• result result2
• IF (vector(i) '1') THEN result
  result1
• END IF
• END LOOP

No range indicated
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Example 4 Type conversion functionfunction call

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• USE work.my_package.all
• ENTITY conv_int2 IS
• PORT ( a IN STD_LOGIC_VECTOR (3 DOWNTO 0)
• y OUT INTEGER RANGE 0 TO 15)
• END conv_int2
• ARCHITECTURE my_arch OF conv_int2 IS
• BEGIN
• y lt conv_integer(a)
• END my_arch

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Procedures
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Procedures Basic Features

• Procedures
• do not return a value
• are called using formal and actual parameters the
  same way as components
• may modify parameters passed to them
• each parameter must have a mode IN, OUT, INOUT
• parameters can be constants (including generics),
  signals (including ports), and variables
• the default for inputs (mode in) is a constant,
  the default for outputs (modes out and inout) is
  a variable
• when passing parameters, range specification
  should be included (for example RANGE for
  INTEGERS, and TO/DOWNTO for STD_LOGIC_VECTOR) but
  not necessary
• procedure calls are statements on their own

33
Procedure syntax

• PROCEDURE procedure_name (ltparameter_listgt) IS
• declarations
• BEGIN
• (sequential statements)
• END function_name

34
Procedure parameters - example

• PROCEDURE p1
• (a, b IN INTEGER SIGNAL c OUT
  STD_LOGIC_VECTOR(2 downto 0)) IS
• BEGIN
• (sequential statements)
• END f1

By default outputs will be avariable, so
explicitly tell itto be a signal
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Procedure calls - examples

• compute_min_max(in1, in2, in3, out1, out2)
• divide(dividend, divisor, quotient, remainder)
• IF (a gt b) THEN
• compute_min_max(in1, in2, in3, out1, out2)
• .......

NOTICE Procedures are stand-alone statements!
36
Example 1 Decoder Procedure in Architecture

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• ENTITY decoder IS port (
• decIn IN STD_LOGIC_VECTOR(1 DOWNTO 0)
• decOut OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
• )
• END decoder

37
Example 1 Decoder Procedure in Architecture
cont'd

• ARCHITECTURE simple OF decoder IS
• PROCEDURE DEC2x4 (inputs in STD_LOGIC_VECTOR(1
  downto 0)
• signal decode out
  STD_LOGIC_VECTOR(3 downto 0)
• ) IS
• BEGIN
• CASE inputs IS
• WHEN "11" gt
• decode lt "1000"
• WHEN "10" gt
• decode lt "0100"
• WHEN "01" gt
• decode lt "0010"
• WHEN "00" gt
• decode lt "0001"
• WHEN others gt
• decode lt "0001"
• END case
• END DEC2x4

By default output will be avariable, so
explicitly tell itto be a signal because
decOutis a signal not a variable
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Procedure versus FunctionsReferences

• Additional differences can be found in Pedroni
• Chapter 11, Functions and Procedures

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Operators
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Operator as a function

• LIBRARY ieee
• USE ieee.std_logic_1164.all
• PACKAGE my_package IS
• FUNCTION "" (a, b STD_LOGIC_VECTOR)
• RETURN STD_LOGIC_VECTOR
• END my_package
• PACKAGE BODY my_package IS
• FUNCTION "" (a, b STD_LOGIC_VECTOR)
• RETURN STD_LOGIC_VECTOR IS
• VARIABLE result STD_LOGIC_VECTOR(a'RANGE)
  
• VARIABLE carry STD_LOGIC
• BEGIN
• carry '0'
• FOR i IN a'REVERSE_RANGE LOOP
• result(i) a(i) XOR b(i) XOR carry
• carry (a(i) AND b(i)) OR (a(i) AND
  carry) OR (b(i) AND carry)
• END LOOP

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Operator Overloading
42
Operator overloading

• Operator overloading allows different argument
  types for a given operation (function)
• The VHDL tools resolve which of these functions
  to select based on the types of the inputs
• This selection is transparent to the user as long
  as the function has been defined for the given
  argument types.

43
Different declarations for the same operator -
Example

• Declarations in the package ieee.std_logic_unsigne
  d
• function "" ( L std_logic_vector
  Rstd_logic_vector) return
  std_logic_vector
• function "" ( L std_logic_vector R
  integer) return std_logic_vector
• function "" ( L std_logic_vector
  Rstd_logic) return std_logic_vector

44
Different declarations for the same operator -
Example

• signal count std_logic_vector(7 downto 0)
• You can use
• count lt count "0000_0001"
• or
• count lt count 1
• or
• count lt count '1'

45
VHDL Pre-Defined Operators
46
Operators (1)
47
Operators (2)
48
Operators (3)
49
VHDL as a Strongly Typed Language
50
Notion of type

• Type defines a set of values and a set of
  applicable operations
• Declaration of a type determines which values can
  be stored in an object (signal, variable,
  constant) of a given type
• Every object can only assume values of its
  nominated type
• Each operation (e.g., and, , ) includes the
  types of values to which the operation may be
  applied, and the type of the result
• The goal of strong typing is a detection of
  errors at an early stage of the design process

51
Example of strong typing

• architecture incorrect of example1 is
• type apples is range 0 to 100
• type oranges is range 0 to 100
• signal apple1 apples
• signal orange1 oranges
• begin
• apple1 lt orange1
• end incorrect

52
Type Classification
53
Classification of data types
54
Integer Types
55
Integer type

• Name integer
• Status predefined
• Contents all integer numbers representable on a
  particular host computer, but at least numbers in
  the range
• (231-1) .. 231-1

56
User defined integer types - Examples

• type day_of_month is range 0 to 31
• type year is range 0 to 2100
• type set_index_range is range 999 downto 100
• constant number_of_bits integer 32
• type bit_index is range 0 to number_of_bits-1

Values of bounds can be expressions, but need to
be known when the model is analyzed.
57
Enumeration Types
58
Predefined enumeration types (1)

• boolean (true, false)
• bit (0, 1)
• character VHDL-87
• 128 7-bit ASCII characters
• VHDL-93
• 256 ISO 8859 Latin-1 8-bit characters

59
Predefined enumeration types (2)

• severity_level (note, warning, error, failure)
• Predefined in VHDL-93 only
• file_open_kind
• (read_mode, write_mode, append_mode)
• file_open_status
• (open_ok, status_error, name_error, mode_error)

60
User-defined enumeration types - Examples

• type state is (S0, S1)
• type alu_function is (disable, pass, add,
  subtract,
• multiply, divide)
• type octal_digit is ('0', '1', '2', '3', '4',
  '5', '6', '7')
• type mixed is (lf, cr, ht, '-', '/', '\')

Each value in an enumeration type must be
either an identifier or a character literal
61
Floating-Point Types
62
Floating point types

• Used to represent real numbers
• Numbers are represented using a significant
  (mantissa) part and an exponent part
• Conform to the IEEE standard 754 or 854
• Minimum size of representation that must be
  supported by the implementation of the VHDL
  standard
• VHDL-2001 64-bit representation
• VHDL-87, VHDL-93 32-bit representation

63
Real literals - examples

• 23.1 23.1
• 46.0E5 46 ? 105
• 1.0E12 1 ? 1012
• 1.234E09 1.234 ? 109
• 34.0e-08 34.0 ? 10-8
• 20.101E5 0.1012 ? 25 (2-12-3) ? 25
• 80.4E-6 0.48 ? 8-6 (4 ? 8-1) ? 8-6
• 160.a5E-8 0.a516 ? 16-8 (10?16-15?16-2) ?
  16-8

Need .0 to prevent compiler errors for real
numbers
64
The ANSI/IEEE standard floating-point number
representation formats
65
User-defined floating-point types - Examples

• type input_level is range -10.0 to 10.0
• type probability is range 0.0 to 1.0
• constant max_output real 1.0E6
• constant min_output real 1.0E-6
• type output_range is range max_output downto
  min_output

66
Attributes of Scalar Types
67
Attributes of all scalar types

• Tleft first (leftmost) value in T
• Tright last (rightmost) value in T
• Tlow least value in T
• Thigh greatest value in T
• Not available in VHDL-87
• Tascending true if T is an ascending range,
  false otherwise
• Timage(x) a string representing the value of x
• Tvalue(s) the value in T that is represented by s

68
Attributes of all scalar types - examples

• type index_range is range 21 downto 11
• index_rangeleft 21
• index_rangeright 11
• index_rangelow 11
• index_rangehigh 21
• index_rangeascending false
• index_rangeimage(14) "14"
• index_rangevalue(20) 20

69
Attributes of discrete types

• Tpos(x) position number of x in T
• Tval(n) value in T at position n
• Tsucc(x) value in T at position one greater
  than position of x
• Tpred(x) value in T at position one less
  than position of x
• Tleftof(x) value in T at position one to the
  left of x
• Trightof(x) value in T at position one to the
  right of x

70
Attributes of discrete types - examples

• type logic_level is (unknown, low, undriven,
  high)
• logic_level'pos(unknown) 0
• logic_level'val(3) high
• logic_level'succ(unknown) low
• logic_level'pred(undriven) low
• logic_level'leftof(unknown) error
• logic_level'rightof(undriven) high

71
Subtypes
72
Subtype

• Defines a subset of a base type values
• A condition that is used to determine which
  values are included in the subtype is called a
  constraint
• All operations that are applicable to the base
  type also apply to any of its subtypes
• Base type and subtype can be mixed in the
  operations, but the result must belong to the
  subtype, otherwise an error is generated.
• Depending on compiler, subtype arrays can only be
  formed from unconstrained array types

73
Predefined subtypes

• natural integers ? 0
• positive integers gt 0
• Not predefined in VHDL-87
• delay_length time ? 0

74
User-defined subtypes - Examples

• subtype bit_index is integer range 31 downto 0
• subtype input_range is real range 1.0E-9 to
  1.0E12

75
Component Configuration
76
Configuration

• If have an entity with multiple architectures,
  must specify which architecture to use when
  instantiating that entity as a component
• If you only have one architecture, do not need to
  configure (also known as bind) the entity to an
  architecture
• Can do this in two ways
• Method 1 Separate configuration section in main
  VHDL code
• A separate section after entity and architecture
  sections
• Aldec Active-HDL 7.2 test bench generator
  automatically creates this
• Method 2 Configurate statement during component
  declaration

77
Method 1 Separate Configuration Section

• library ieee
• use ieee.std_logic_arith.all
• use ieee.std_logic_unsigned.all
• use ieee.std_logic_1164.all
• entity poweroffour_tb is
• end poweroffour_tb
• architecture TB_ARCHITECTURE of poweroffour_tb is
• component poweroffour
• port(X in std_logic_vector(1 downto 0)
• Y out std_logic_vector(6 downto 0) )
• end component
• signal X std_logic_vector(1 downto 0)
• signal Y std_logic_vector(6 downto 0)
• begin
• UUT poweroffour
• port map (X gt X,Y gt Y)

78
Method 1 Separate Configuration Section cont'd

• process
• begin
• x lt "11"
• wait
• end process
• end TB_ARCHITECTURE
• configuration TESTBENCH_FOR_poweroffour of
  poweroffour_tb is
• for TB_ARCHITECTURE
• for UUT poweroffour
• use entity work.poweroffour(behavioral)
• end for
• end for
• end TESTBENCH_FOR_poweroffour

79
Method 2 Configurate statement during component
declaration

• library ieee
• use ieee.std_logic_arith.all
• use ieee.std_logic_unsigned.all
• use ieee.std_logic_1164.all
• entity poweroffour_tb is
• end poweroffour_tb
• architecture TB_ARCHITECTURE of poweroffour_tb is
• component poweroffour
• port(X in std_logic_vector(1 downto 0)
• Y out std_logic_vector(6 downto 0) )
• end component
• for all poweroffour use entity
  work.poweroffour(behavioral)
• signal X std_logic_vector(1 downto 0)
• signal Y std_logic_vector(6 downto 0)
• begin
• UUT poweroffour
• port map (X gt X,Y gt Y)

80
VHDL Modeling of Microprocessors
81
Single Versus General Purpose Processors

• Thus far we have designed single-purpose
  processors
• The controller is "hard-coded" to perform one
  task only
• Examples bit-count, log2 calculation, sort,
  stream cipher
• A general purpose processor is able to perform
  many tasks
• The control unit is not "hard-coded" to perform a
  specific task
• Rather it reads instructions from memory and
  executes them
• Can implement any function as long as the
  instruction set supports it
• Due to its general nature, functions executing on
  general purpose processors are usually slower
  than on single-purpose processors
• "Software implementation" ? funciton run on
  general purpose processor
• "Hardware implementation" ? function run on
  single purpose processor
• Many of the following come from the excellent
  book
• Vahid and Givargis, "Embedded System Design A
  Unified Hardware/Software Introduction"

82
Introduction

• General-Purpose Processor
• Processor designed for a variety of computation
  tasks
• Low unit cost, in part because manufacturer
  spreads NRE (non-recurring engineering cost) over
  large numbers of units
• Motorola sold half a billion 68HC05
  microcontrollers in 1996 alone
• Carefully designed since higher NRE is acceptable
• Can yield good performance, size and power
• Low NRE cost, short time-to-market/prototype,
  high flexibility
• User just writes software no processor design
• a.k.a. microprocessor micro used when they
  were implemented on one or a few chips rather
  than entire rooms

Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"
83
Basic Architecture

• Control unit and datapath
• Note similarity to single-purpose processor
• Key differences
• Datapath is general
• Control unit doesnt store the algorithm the
  algorithm is programmed into the memory

Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"
84
Datapath Operations

• Load
• Read memory location into register

Processor
Control unit
Datapath
ALU
Controller
Control /Status

• ALU operation
• Input certain registers through ALU, store back
  in register

Registers
10
11
IR
PC

• Store
• Write register to memory location

I/O
...
Memory
10
...
11
Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"
85
Control Unit

• Control unit configures the datapath operations
• Sequence of desired operations (instructions)
  stored in memory program
• Instruction cycle broken into several
  sub-operations, each one clock cycle, e.g.
• Fetch Get next instruction into IR
• Decode Determine what the instruction means
• Fetch operands Move data from memory to datapath
  register
• Execute Move data through the ALU
• Store results Write data from register to memory

Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"
86
Control Unit Sub-Operations

• Fetch
• Get next instruction into IR
• PC program counter, always points to next
  instruction
• IR holds the fetched instruction

Processor
Control unit
Datapath
ALU
Controller
Control /Status
Registers
IR
PC
R0
R1
100
load R0, M500
I/O
...
Memory
load R0, M500
100
10
500
inc R1, R0
101
...
501
store M501, R1
102
Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"
87
Control Unit Sub-Operations

• Decode
• Determine what the instruction means

Processor
Control unit
Datapath
ALU
Controller
Control /Status
Registers
IR
PC
R0
R1
100
load R0, M500
I/O
...
Memory
load R0, M500
100
10
500
inc R1, R0
101
...
501
store M501, R1
102
Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"
88
Control Unit Sub-Operations

• Fetch operands
• Move data from memory to datapath register

Processor
Control unit
Datapath
ALU
Controller
Control /Status
Registers
10
IR
PC
R0
R1
100
load R0, M500
I/O
...
Memory
load R0, M500
100
10
500
inc R1, R0
101
...
501
store M501, R1
102
Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"
89
Control Unit Sub-Operations

• Execute
• Move data through the ALU
• This particular instruction does nothing during
  this sub-operation

Processor
Control unit
Datapath
ALU
Controller
Control /Status
Registers
10
IR
PC
R0
R1
100
load R0, M500
I/O
...
Memory
load R0, M500
100
10
500
inc R1, R0
101
...
501
store M501, R1
102
Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"
90
Control Unit Sub-Operations

• Store results
• Write data from register to memory
• This particular instruction does nothing during
  this sub-operation

Processor
Control unit
Datapath
ALU
Controller
Control /Status
Registers
10
IR
PC
R0
R1
100
load R0, M500
I/O
...
Memory
load R0, M500
100
10
500
inc R1, R0
101
...
501
store M501, R1
102
Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"
91
Instruction Cycles
PC100
clk
100
Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"
92
Instruction Cycles
PC100
Fetch ops
Store results
Fetch
Decode
Exec.
clk
PC101
clk
10
101
Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"
93
Instruction Cycles
PC100
Fetch ops
Store results
Fetch
Decode
Exec.
clk
PC101
Fetch ops
Store results
Fetch
Decode
Exec.
clk
11
10
102
PC102
clk
Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"
94
Architectural Considerations

• N-bit processor
• N-bit ALU, registers, buses, memory data
  interface
• Embedded 8-bit, 16-bit, 32-bit common
• Desktop/servers 32-bit, even 64
• PC size determines address space

Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"
95
Architectural Considerations

• Clock frequency
• Inverse of clock period
• Must be longer than longest register to register
  delay in entire processor
• Memory access is often the longest

Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"
96
Pipelining Increasing Instruction Throughput
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Wash
Non-pipelined
Pipelined
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Dry
Time
Time
non-pipelined dish cleaning
pipelined dish cleaning
Fetch-instr.
1
2
3
4
5
6
7
8
Decode
1
2
3
4
5
6
7
8
Fetch ops.
1
2
3
4
5
6
7
8
Pipelined
Execute
1
2
3
4
5
6
7
8
Instruction 1
Store res.
1
2
3
4
5
6
7
8
Time
pipelined instruction execution
Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"
97
Superscalar and VLIW Architectures

• Performance can be improved by
• Faster clock (but theres a limit)
• Pipelining slice up instruction into stages,
  overlap stages
• Multiple ALUs to support more than one
  instruction stream
• Superscalar
• Scalar non-vector operations
• Fetches instructions in batches, executes as many
  as possible
• May require extensive hardware to detect
  independent instructions
• VLIW each word in memory has multiple
  independent instructions
• Relies on the compiler to detect and schedule
  instructions
• Currently growing in popularity

Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"
98
Two Memory Architectures

• Princeton
• Fewer memory wires
• Harvard
• Simultaneous program and data memory access

Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"
99
Cache Memory

• Memory access may be slow
• Cache is small but fast memory close to processor
• Holds copy of part of memory
• Hits and misses

Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"
100
Assembly-Level Instructions

• Instruction Set
• Defines the legal set of instructions for that
  processor
• Data transfer memory/register,
  register/register, I/O, etc.
• Arithmetic/logical move register through ALU and
  back
• Branches determine next PC value when not just
  PC1

Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"
101
A Simple (Trivial) Instruction Set
Assembly instruct.
First byte
Second byte
Operation
MOV Rn, direct
0000
Rn
direct
Rn M(direct)
MOV direct, Rn
0001
Rn
direct
M(direct) Rn
Rm
MOV _at_Rn, Rm
0010
Rn
M(Rn) Rm
MOV Rn, immed.
0011
Rn
immediate
Rn immediate
ADD Rn, Rm
0100
Rm
Rn
Rn Rn Rm
SUB Rn, Rm
0101
Rm
Rn Rn - Rm
Rn
JZ Rn, relative
0110
Rn
relative
PC PC relative (only if Rn is 0)
opcode operands
Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"
102
Addressing Modes
Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"
103
Sample Program
Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"
104
Running a Program

• If development processor is different than
  target, how can we run our compiled code? Two
  options
• Download to target processor
• Simulate
• Simulation
• One method Hardware description language
• But slow, not always available
• Another method Instruction set simulator (ISS)
• Runs on development processor, but executes
  instructions of target processor

Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"
105
Designing a General Purpose Processor

• Not something an embedded system designer
  normally would do
• But instructive to see how simply we can build
  one top down
• Remember that real processors arent usually
  built this way
• Much more optimized, much more bottom-up design

Declarations bit PC16, IR16 bit
M64k16, RF1616
Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"
106
Simple Microprocessor Design
107
Architecture of a Simple Microprocessor

• Storage devices for each declared variable
• register file holds each of the variables
• Functional units to carry out the FSMD operations
• One ALU carries out every required operation
• Connections added among the components ports
  corresponding to the operations required by the
  FSM
• Unique identifiers created for every control
  signal

Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"
108
A Simple Microprocessor
PCclr1
Reset
PC0
IRMPC PCPC1
MS10 Irld1 Mre1 PCinc1
Fetch
Decode
from states below
RFwarn RFwe1 RFs01 Ms01 Mre1
Mov1
RFrn Mdir
to Fetch
op 0000
RFr1arn RFr1e1 Ms01 Mwe1
Mov2
Mdir RFrn
0001
to Fetch
RFr1arn RFr1e1 Ms10 Mwe1
Mov3
Mrn RFrm
0010
to Fetch
RFwarn RFwe1 RFs10
Mov4
RFrn imm
0011
to Fetch
RFwarn RFwe1 RFs00 RFr1arn
RFr1e1 RFr2arm RFr2e1 ALUs00
Add
RFrn RFrnRFrm
0100
to Fetch
RFwarn RFwe1 RFs00 RFr1arn
RFr1e1 RFr2arm RFr2e1 ALUs01
Sub
RFrn RFrn-RFrm
0101
to Fetch
PCld ALUz RFrlarn RFrle1
Jz
PC(RFrn0) ?rel PC
0110
to Fetch
FSM operations that replace the FSMD operations
after a datapath is created
FSMD
You just built a simple microprocessor!
Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"
109
Simple Microprocessor Architecture
Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"
110
Simple Microprocessor VHDL Hierarchy
Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"
111
Simple Microprocessor ExampleFibonacci Sequence
112
Fibonacci Sequence on Microcontroller

• Fibonacci Sequence
• Equation
• Each number is the summation of the previous two
  numbers
• Sequence 0, 1, 1, 2, 3, 5, 8, 13, 21, 34, 55,
  89, 144, 233, etc.
• Instead of implementing single-purpose Fibonacci
  sequence generator as we have been doing thus
  far, implement it as a sequence of instructions
  in memory
• The simple microprocessor will execute these
  instructions

113
Code snippet from memory.vhd showing instructions

• -- program to generate 10 fibonacci numbers
• 0 gt "0011000000000000", -- mov R0, 0
• 1 gt "0011000100000001", -- mov R1, 1
• 2 gt "0011001000110100", -- mov R2, 52
• 3 gt "0011001100000001", -- mov R3, 1
• 4 gt "0001000000110010", -- mov M50, R0
• 5 gt "0001000100110011", -- mov M51, R1
• 6 gt "0001000101100100", -- mov M100, R1
• 7 gt "0100000100000000", -- add R1, R0
• 8 gt "0000000001100100", -- mov M100, R0
• 9 gt "0010001000010000", -- mov MR2, R1
• 10 gt "0100001000110000", -- add R2, R3
• 11 gt "0000010000111011", -- mov R4, M59
• 12 gt "0110010000000101", -- jz R4, 6
• 13 gt "0111000000110010", -- output M50
• 14 gt "0111000000110011", -- ,, M51
• 15 gt "0111000000110100", -- ,, M52
• 16 gt "0111000000110101", -- ,, M53
• 17 gt "0111000000110110", -- ,, M54

Source Vahid and Givargis, "Embedded System
Design A Unified Hardware/Software Introduction"