Title: Embedded Systems Design EEE502M2 Lesson 4 An Introduction to the HC11 Microcontroller
1Embedded Systems DesignEEE502M2Lesson 4 An
Introduction to the HC11 Microcontroller
2The Motorola 68HC11 Microcontroller
- Recommended Text
- HW Huang
- MC68HC11 An Introduction, Software and
Hardware Interfacing - West Publishing, 1996
- ISBN 0-314-06735-3
3See Also
- AUTHOR(S) Bannatyne, R. Viot, G.
- TITLE Microcontrollers - Part I
- PAGE pp. 238-249
- CONFERENCE Conference -- 1998 Oct Seattle WA
- SOURCE Northcon '98
- SPONSOR IEEE.
- PUBLISHER IEEE 1998
- JOURNAL NORTHCON 1998
- ISBN 0780350758 0780350766 0780350774
4See Also
- AUTHOR(S) Bannatyne, R. Viot, G.
- TITLE Microcontrollers - Part II
- PAGE pp. 250-254
- CONFERENCE Conference -- 1998 Oct Seattle WA
- SOURCE Northcon '98
- SPONSOR IEEE.
- PUBLISHER IEEE 1998
- JOURNAL NORTHCON 1998
- ISBN 0780350758 0780350766 0780350774
5And
- AUTHOR(S) Bannatyne, R. Viot, G.
- TITLE Intro to Microcontrollers - Module A
- PAGE pp. 564-575
- CONFERENCE Conference -- 1997 Nov Santa
Clara CA - SOURCE Wescon
- PUBLISHER IEEE 1997
- JOURNAL WESCON CONFERENCE RECORD 1095-791X 1997
- ISBN 0780343034 0780343042 0780343050
6The HC11 Microcontroller
- Developed in 1986
- More than 50 family members (refer to HUANG p157,
Table 4.1) - Family members differ in on-chip features
- Differ in I/O capabilities
- Concentrate on HC11A1 and F1 members
7HC11A1 Features
- On-chip static RAM
- On-chip EEPROM
- On-chip ROM
- Programmable Timer
- 3 Input-capture functions
- 5 Output compare functions
- 8-bit pulse accumulator
8Features Contd.
- Serial Comms interface (SCI)
- Serial Peripheral interface (SPI)
- Real-time interrupt circuit (RTI)
- Computer Operating Properly watchdog (COP) system
- On-chip A/D converter
9Block Diagram
- See figure 4.1 for HC 11E1 block diagram
- Note Ports A,B,C,D,E
- Port A Input/Output mixed
- Port B Output
- Port C Input/Output
- Port D Input/output
- Port E Input
10(No Transcript)
1168HC11 Registers
- Two classes of registers
- CPU general purpose arithmetic etc
- I/O control operation of I/O operations,
peripherals - I/O registers treated as memory locations when
accessed - CPU registers do not occupy space in memory map
12CPU Registers see figure 4.2
- A and B general purpose 8-bit accumulators
- May be combined to form D (double, 16 bit)
- IX 16 bit index register
- IY as for IX
- SP 16 bit stack pointer
- PC 16 bit program counter
13HC11 CPU Registers
7 Accumulator A 0
7 Accumulator B 0
15 Double Accumulator D
0
15 Index Register IX
0
15 Index Register IY
0
15 Stack Pointer SP
0
15 Program Counter PC
0
Figure 4.2
14CCR Condition Code Register
S X H I N Z V C
Stop Carry X Interrupt Overflow Half
Carry Zero Interrupt Negative
15Addressing Modes
- Immediate e.g. LDAA 22h
- Direct ADDA 00h
- Extended mode e.g. LDAA 1000h
- Indexed e.g. ADDA 10,X
- Inherent e.g. ABA or INX
- Relative only used for branches
16Instruction Set
- Features usual set of instructions
- Arithmetic e.g. ADDA, ADDB, SUBA
- Data Movement e.g. LDAA, LDAB, TAB
- Branch BRA, BCC
- Store STAA, STAB
- Shift LSRD, LSRA
- See Huang pp491-604
17Examples of HC11 Instructions
- See figure 4.3 for LOAD instructions
- See figure 4.4 for ADD instructions
- See figure 4.5 for SUB instructions
18Figure 4.3 LOAD Instructions
- LDAA 10
- load accumulator A with 10 decimal
- LDAB 1000h
- copy contents of memory location 1000 hex into
accumulator B - LDX 1234
- load 1234 into index register X
- LDS 456
- put 456 decimal into stack pointer SP
19Figure 4.4 ADD Instructions
- ABA add contents of accum. A to contents of
accum. B and store result in A - ABY add contents of accum. B to contents of 16
bit index register Y and store result in Y - ADDB 20h add contents of memory address 20 hex
to contents of accum. B and store result in B
20Figure 4.5 SUB Instructions
- SBA subtract contents of accum. B from contents
of accum. A and store result in A - SUBA 10 subtract 10 decimal from accum. A
contents and store result in A - SUBB 10 subtract 10 decimal from accum. B
contents and store result in B - SUBD 23 subtract 23 decimal from contents of
double accum. D and store result in D
21HC11 Operating Modes
- Four Possible Modes
- expanded
- single-chip
- special bootstrap
- special test
- Controlled by MODA, MODB pins
22Controlling the Mode
23Modes
- Special Test used by Motorola at production test
stage - Special Bootstrap Used to load a program into
internal on-chip SRAM - Single-chip No external additions or peripherals
- Expanded allows for external RAM, ROM etc
2468HC11 Interrupts
- HC11 supports 16 hardware interrupts
- Two software interrupts
- Three resets
- See figure 4.6
- In A series, first 15 interrupts (e.g. from SCI
to IRQ) can be masked by setting I bit in CCR - All on-chip interrupt sources maskable by local
control bits.
25Figure 4.6
26Interrupts Contd.
- SWI software interrupt is non-maskable
- illegal op-code also non-maskable
- IRQ and XIRQ only external interrupt sources
- Edge or level triggering selectable by user for
IRQ interrupt, using OPTION register - Priority of each maskable interrupt source is
fixed
27Interrupt Programming
- Three steps
- Write interrupt handlers
- Set up interrupt vector table
- Set global and local interrupt enable bits
28Low Power Mode
- HC11 uses CMOS technology
- Power consumption related to clock speed
- Slowing down chip reduces power consumed
- Two instructions of interest i.e. WAIT and STOP
- WAIT low power, oscillator still running
- STOP lowest power, all internal processing halted
29Parallel I/O Ports68HC11A1
- 40 I/O pins
- Five I/O ports
- All pins serve multiple functions, depending on
mode and control registers - C and D are general purpose I/O, under control of
associated DDRs - A,B, E are fixed direction (except Port A, pin 7)
so no DDRs
30Referring to I/O Ports
- Each port has an associated data register
- If you include lthc11.hgt in your C source file you
may refer to the ports by name without having to
define them yourself - e.g.
- porta porta 20
- or
- ldaa porta
31Addresses of Port Data Registers
- See Appendix 1 of Notes
- Examples are
- porta 1000h
- portb 1004h
- portc 1003h
- portd 1008h
- porte 100ah
32The 68HC11 Timer Functions
- Many applications which require timing
- delay creation and measurement
- event counting
- time of day tracking
- periodic interrupt for routine tasks
- waveform generation
- pulse width calculation
- See figure 4.7
33Figure 4.7 Main Timer
3468HC11 Timer Includes
- 16 bit free running main timer
- Input Capture facility can latch current count
on receipt of external pulse - Output Compare allows for the generation of an
event (e.g. interrupt, sets a flag, sets a pin
high or low) when current count equals value in
compare register
35Timer Contd.
- Real time interrupt for tasks requiring
repetitive but time-critical attention -- RTI
generates an interrupt, interrupt service routine
services task - Computer Operating Properly resets computer
system if program fails to take care of COP
refresh within a fixed time limit
36Timer Contd.
- 8-bit Pulse Accumulator used for event counting
within a specified time window - Timer system involves a large number of registers
which need to be set up before timer systems may
be used.
37Free Running Timer TCNT
- See figure 4.8
- Driven by E signal, scaled by pre-scalerr
(1,4,8,16) - PR0,PR1 set pre-scaler in TMSK2 register
- Cleared to 0 by reset
- Read only register
38Figure 4.8 Main TimerBlock Diagram
Interrupt request
TOI
TOF
TCNT (L)
TCNT (H)
Pre-scaler Divide by 1, 4, 8,16
16 bit free running counter
MCU E clock
16 bit timer bus
39Main Timer contd.
- TOF flag set in TFLG2 when timer goes from FFFF
to 0000 - TOF cleared by writing a 1 to it
- Interrupt enabled on overflow by setting TOI bit
of TMSK2 - See next slide for contents of TFLG2 and TMSK2
40TFLG2 and TMSK2 Registers
7
6
5
3
2
1
0
Bit
4
PR0TMSK2
TOI
RTII
PAOII
PAII
O
O
PR1
PR0
TOF
RTIF
PAOVF
PAIF
TFLG2
41Effect of Pre-Scaler
- PR1 PR0 Period (2MHz clock)
- 0 0 32.77 ms
- 0 1 131.1 ms
- 1 0 262.1 ms
- 1 1 524.3 ms
42Input Capture Functions
- Allows arrival time of events to be recorded
- Arrival time recorded as main counter count
- Need to be careful of overflows i.e. if longer
than FFFF - Can look for rising or falling edge to trigger
latch of count - See next slide for block diagram
43Input Capture Block Diagram
Signal on ICx pin
Edge detection logic
ICxF
16 bit main timer
Interrupt request
Timer bus
ICxl
TICx
44Three Input Capture Channels
- Arrival time of edge stored in input-capture
register (TIC1, TIC2 or TIC3) - TIC1 located at 1010/1011h
- TIC2 located at 1012/1013h
- TIC3 located at 1014/1015h
- Not affected by reset, cannot be written to by
software
45Input Capture contd.
- PA0, PA1, PA2 are input only
- Used for input capture channels 1,2,3
respectively when enabled. - If disabled, become general purpose input pin
- See diagram 4.1
46Input Capture Registers
- Use TCTL2 at 1021h for selection of edges
- EDGxB EDGxA
- 0 0 capture disabled
- 0 1 capture on rising edge
- 1 0 capture on falling edge
- 1 1 capture on any edge
47TCTL2 RegisterSetting up Edges for Capture
EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A
TCTL2
48TFLG1 Register At 1023HFlags set on
CaptureFlag set on captureFlag cleared by
writing a 1 to it
7 6 5 4 3
2 1 0
OC1F OC2F OC3F OC4F OC5F IC1F IC2F IC3F
49Interrupt Request
- Optionally generate an interrupt when an edge is
captured - Such interrupts enables or disabled via mask
register TMSK1 at 1022h
50TMSK1 Register At 1022HEnable/ Disable
Interrupts on CaptureInterrupt may be generated
if bit set
7 6 5 4 3
2 1 0
OC1I OC2I OC3I OC4I OC5I IC1I IC2I IC3I
51Redirection of Interrupt Vectors on Experimental
Board
- The application board monitor program re-directs
the interrupt vectors to different locations as
follows (all hex) - Channel Pin HC11 Location EVB Location
- IC1 PA2 FFEE-FFEF
- IC2 PA1 FFEC-FFED See Application Board
Manual - IC3 PA0 FFEA-FFEB
52Output Compare Functions
- 68HC11 has
- 16 bit comparator
- 16 bit compare register (TOCx)
- output action pin (OCx, can be pulled low or
high) - Interrupt request logic
- Forced compare function (FOCx)
- Control logic
53Output Compare Block Diagram
OCxI
Interrupt request
16 bit comparator
OCx Pin
OCxF
Timer bus
Pin Control Logic
FOCx
TOCx
54Using the Output Compare Functions
- Make a copy of current contents of free running
timer - Add to this value equal to required delay
- Store sum in Output Compare register
- Specify action on equality (pull high, pull low,
toggle) by programming TCTL1 register
55Five Output Compare Channels
- TOC1,TOC2,TOC3,TOC4,TOC5
- TOC1 located at 1016/1017h
- TOC2 located at 1018/1019h
- TOC3 located at 101A/101Bh
- TOC4 located at 101C/101Dh
- TOC5 located at 101E/101Fh
56TCTL1 Register At 1020HOutput Compare
ActionInterrupt may be generated if bit set
7 6 5 4 3
2 1 0
OM2 OL2 OM3 OL3 OM4 OL4 OM5 OL5
57Action on Successful Compare
- OMx OLx
- 0 0 OCx does not affect pin
- 0 1 Toggle OCx pin
- 1 0 Clear OCx pin
- 1 1 Set OCx pin
58Uses of Output Compare
- Popular uses are generation of single pulse,
square wave, specific delay - Example Use pin OC2 to generate a 1KHz signal
with 40 duty cycle. Assume E is 2MHz and
pre-scaler is 1
59Appendix 1 I/O Register Addresses (Partial
Listing) in Hex (see datasheet for full listings)
- 103F Config 103D Init
- 1039 Option 1025 TFLG2
- 1024TMSK2 1020TCTL1
- 100FTCNT 100ETCNT
- 100AportE 1009DDRD
- 1008portD 1007DDRC
- 1004portB 1003portC
- 1000portA 1002PIOC
60Getting the HC11F1 Datasheet
- Access Motorolas general MCU website
- http//www.mcu.motsps.com/hc11/index.html
- Datasheets
- http//mot-sps.com/mcu/documentation/pdf/f1.pdf
for F1 - http//mot-sps.com/mcu/documentation/pdf/a8.pdf
for A8