Computer Architecture Chapter 2 Instructions: Language of the Computer

1
Computer ArchitectureChapter 2 Instructions
Language of the Computer

• Yu-Lun Kuo ???
• Department of Computer Science and Information
  Engineering
• Tunghai University, Taichung, Taiwan R.O.C.
• sscc6991_at_gmail.com
• http//www.csie.ntu.edu.tw/d95037/

2
Introduction

• Computer designers have a common goal
• Find a language that makes it easy to build
  hardware and the compiler
• Maximizing performance and minimizing cost
• Instruction Set
• Language of the machine, its vocabulary is called
  an instruction set
• The vocabulary of commands understood by a given
  architecture.

3
Introduction

• Well be working with the MIPS instruction set
  architecture
• Similar to other architectures developed since
  the 1980's
• Almost 100 million MIPS processors manufactured
  in 2002
• Used by NEC, Nintendo, Cisco, Silicon Graphics,
  and Sony.
• Stored-program concept
• The idea that instructions and data of many types
  can be stored in memory as numbers, leading to
  the stored program computer.

4
CPU Manufacturer (1/2)

• Intel Pentium IV, IA-64
• AMD K6-3, K7, Duron, Athron
• IBM PowerPC
• Sun SPARC
• HP PA-RISK, IA-64
• DEC Alpha
• MIPS MIPS (Book)
• VIA/Cyrix C7 series
• Motorola DragonBall
• Used in Palm handheld devices

5
CPU Manufacturer (2/2)
6
RISC (Reduced Instruction Set Computer)

• RISC philosophy
• fixed instruction lengths
• load-store instruction sets
• limited addressing modes
• limited operations
• Instruction sets are measured by how well
  compilers use them as opposed to how well
  assembly language programmers use them

Design goals speed, cost (design, fabrication,
test, packaging), size, power consumption,
reliability, memory space
7
MIPS Instruction Set Architecture (ISA)

• Instruction Categories
• Computational
• Load/Store
• Jump and Branch
• Floating Point
• Memory Management
• Special

Registers
R0 - R31
PC
HI
LO
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MIPS arithmetic

• HLL ? MIPS Assembly ? MIPS Machine
• High Level Language Statements ? Assembly
  Language Translation
• The translation process includes
• Assigning variables in high level language
  statement into registers
• Translation into assembly

9
Operations of MIPS

• All instructions have 3 operands
• Operand order is fixed (destination first)
• Example
• C code a b c
• MIPS code add a, b, c

10
MIPS Arithmetic Instructions

• MIPS assembly language arithmetic statement
• add t0, s1, s2
• sub t0, s1, s2
• Each arithmetic instruction performs only one
  operation
• Each arithmetic instruction fits in 32 bits and
  specifies exactly three operands
• destination ? source1 op source2

• Operand order is fixed (destination first)

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Operations of MIPS

• Of course this complicates some things...
  C code a b c d MIPS code add a, b,
  c add a, a, d
• Operands must be registers
• Only 32 registers provided. (MIPS)
• Each register contains 32 bits. (32bits 4bytes
  word)

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Example

• Place the sum of variables b, c, d, and e into
  variable a
• add a, b, c
• add a, a, d
• add a, a, e a bcde
• Takes three instructions to take sum of four
  variables
• is comments for the human reader

13
Operands of MIPS

• All instructions have 3 operands
• The natural number of operands for an operation
  like addition is threerequiring every
  instruction to have exactly three operands, no
  more and no less, conforms to the philosophy of
  keeping the hardware simple
• Each line of this language can contain at most
  one instruction

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Operands of MIPS

• Design Principle 1 Simplicity favors regularity
• Simple ? fixed number of operand
• ? regularity

Hardware for a variable number of operands is
more complicated than hardware for a fixed number
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Compiling C into MIPS

• C (Java) program contains the five variables a,
  b, c, d, and e
• a b c
• d a e
• MIPS instruction

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Example

• Complex statement contains five variables
• f (g h) (i j)
• MIPS code add t0, g, h temporary
• add t1, i, j
• sub f, t0, t1

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Operands of MIPS

• Design Principle 2 Smaller is faster.
• A very large number of registers may increase the
  clock cycle time simply.
• Because it takes electronic signals longer when
  they must travel farther
• Arithmetic instructions operands must be
  registers, only 32 registers are provided.

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Operands of MIPS (Registers)

• Simply write instructions using numbers for
  register, from 0 to 31
• Following a dollar sign to represent a register
• Use s0, s1, for registers that correspond to
  variables (variable registers)
• Use t0, t1, for temporary registers

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Example

• Compilers job to associate program variables
  with registers
• f (g h) - (i j)
• Variable f, g, h, i and j are assigned to the
  registers s0, s1, s2, s3, s4
• add t0,s1,s2
• add t1,s3,s4
• sub s0,t0,t1

20
Registers vs. Memory

• The processor can keep only a small amount of
  data in registers, but computer memory contains
  millions of data elements

21
Registers

• Data is more useful in a register
• MIPS registers take both less time to access and
  have higher throughput than memory
• Faster to access
• Highest performance
• Simpler to use

22
Memory Operands

• Data transfer instructions
• Arithmetic operations occur only on registers in
  MIPS, thus, MIPS must include instructions that
  transfer data between memory and registers.
• Access a word in memory (supply memory address)
• lw and sw
• Addressing (??)
• A value used to delineate the location of a
  specific data element within a memory array.

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Memory Organization

• Viewed as a large, single-dimension array, with
  an address.
• A memory address is an index into the array
• Byte addressing means that the index points to
  a byte of memory.

...
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Memory Organization

• The constant in the data transfer instruction is
  called offset
• The register added to form the address is called
  base register
• Copy data from memory to register is called load
• Register used to access memory
• MIPS name for this instruction is lw
• Standing for load word

Base offset
offset
Base address (s3)
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Operand is in Memory (Example)

• A is an array of 100 bytes
• The variables g and h with registers s1 and s2
• The starting address (base address) of the array
  is in s3
• C code g h A8 MIPS code lw t0,
  8(s3) add s1,s2,t0

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Memory Organization

• Bytes are nice, but most data items use larger
  words, for MIPS, a word is 32 bits or 4 bytes.
• 232 bytes with byte addresses from 0 to 232-1
• Words are aligned

Alignment restriction
0
32 bits of data
4
32 bits of data
8
32 bits of data
12
32 bits of data
...
Registers hold 32 bits of data
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Endian Problem

• Since 8-bit bytes are so useful, most
  architectures address individual bytes in memory
• The memory address of a word must be a multiple
  of 4 (alignment restriction)
• Big Endian leftmost byte is word address
• IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA
• Little Endian rightmost byte is word address
• Intel 80x86, DEC Vax, DEC Alpha (Windows NT)

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Compiling Using Load and Store

• Load and store instructions
• C code A12 h A8MIPS code lw t0,
  32(s3) add t0, s2 ,t0 sw t0,
  48(s3)
• Can refer to registers by name (e.g., s2, t0)
  instead of number
• g?s1 register, h?s2 register
• s3 is Array As base register
• Remember arithmetic operands are registers, not
  memory! Cannot write
• add 48(s3), s2, 32(s3)

A12 A10 A8
s3 412
s3 48
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Example

• Example
• g?s1 register, h?s2 register, i? s4
• s3 is Array As base register
• C code g h Ai

add t1, s4, s4 add t1, t1, t1
t1 gets 4i add t1, t1, s3 lw
t0, 0(t1) t0 gets Ai add
s1, s2, t0
Ai A0
s3 4i
s3
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Emphasis

• Load Memory ? register (lw)
• Store register ? memory (sw)

Base Offset
Offset
Base
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MIPS Register Convention
Register 1 (at) reserved for assembler, 26-27
for operating system
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Compiling Using Load and Store
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So far We Learn
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So far We Learn

• Design Principle 3 Make the common case fast
• MIPS
• loading words but addressing bytes
• arithmetic on registers only
• Instruction Meaning
• add s1,s2,s3 s1 s2 s3
• sub s1,s2,s3 s1 s2 s3
• lw s1,100(s2) s1 Memorys2100
• sw s1,100(s2) Memorys2100 s1

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Spilling Register

• Many programs have more variable than computers
  have registers
• 32 registers in MIPS
• Compiler tries to keep the most frequently used
  variables in registers and places the rest in
  memory
• The process of putting less commonly used
  variables (needed later) into memory is called
  spilling registers

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Representing Instructions

• Instructions, like registers and words of data,
  are also 32 bits long
• Example add t1,s1,s2
• Registers have numbers (0, 1, 2, , 31)
• s0 to s7 map onto registers 16 to 23
• t0 to t7 map onto registers 8 to 15
• t19, s117, s218
• Instruction Format 000000 10001 10010 01001
  00000 100000 op rs rt rd shamt funct
• Can you guess what the field names stand for?

R format
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Representing Instructions

• Binary representation
• Instruction format
• MIPS instructions are 32 bits long
• Simplicity favors regularity

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Representing Instructions
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Representing Instructions
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MIPS Fields

• Arithmetic Instruction Format (R format)

add t0, s1, s2
op 6-bits opcode that specifies the
operation rs 5-bits register file address of the
first source operand rt 5-bits register file
address of the second source operand rd 5-bits re
gister file address of the results
destination shamt 5-bits shift amount (for shift
instructions) funct 6-bits function code
augmenting the opcode
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Representing Instructions

• Machine Language
• Binary representation used for communication
  within a computer system
• Instruction Format
• A form of representation of an instruction
  composed of fields of binary numbers.

42
MIPS Memory Access Instructions

• MIPS has two basic data transfer instructions for
  accessing memory
• lw t0, 4(s3) load word from memory
• sw t0, 8(s3) store word to memory
• The load word instruction must specify two
  registers and a constant
• Constant with the load word instruction would be
  limited to only 25 or 32
• 5 bit-field is too small to be useful (often much
  larger than 32)

43
One Size Fits All?

• The compromise chosen by the MIPS designer
• Keep all instructions the same length
• Requiring different kinds of instruction formats
  for different kinds of instruction
• Design Principle 4 Good design demands good
  compromises
• We have 3 types of instructions
• R-type (register)
• I-type (immediate)
• J-type (jump)

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Representing Instructions
45
Machine Language Load Instruction

• Load/Store Instruction Format (I format)
• A 16-bit field meaning access is limited to
  memory locations within a region of ?215 or
  32,768 bytes (?213 or 8,192 words) of the address
  in the base register
• Note that the offset can be positive or negative

lw t0, 24 (s2)
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MIPS Instruction Encoding
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Translate MIPS into Machine Language

• EX. t1 has the base of array A, s2 is h
• A300 h A300 complied into
• lw t0, 1200(t1)
• add t0, s2, t0 t0 gets hA300
• sw t0, 1200(t1)

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Translate MIPS into Machine Language

• Binary representation

op
rs
rt
address
100011
01001
01000
0000 0100 1011 0000
op
rs
rt
rd
shamt
funct
000000
10010
01000
01000
00000
100000
op
rs
rt
address
101011
01001
0000 0100 1011 0000
01000
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So Far We Learn
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Stored Program Concept

• Instructions are bits
• Programs are stored in memory to be read or
  written just like data
• Fetch and Execute Cycle
• Instructions are fetched and put into a special
  register (Instruction Register)
• Bits in the register control the subsequent
  actions
• Fetch the next instruction and continue

51
Logical Operations

• MIPS provides the usual bitwise logical
  instructions that are also in x86
• and
• or
• nor (not or)
• and immediate
• or immediate
• shift left logical
• shift right logical
• Table 2.10 shows a summary

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Logical Operations (MIPS instructions)
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Shift Operations

• Shift left logical (sll)
• 0000 0000 0000 1001 9
• 0000 0000 1001 0000144
• sll t2,s0,4 reg t2 reg s0 ltlt 4 bits
• Shift right logical (srl)

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and/or/not/nor

• Example
• 0000 0000 0000 0000 0000 1101 0000 0000 (t2)
• 0000 0000 0000 0000 0011 1100 0000 0000 (t1)
• and t0, t1, t2
• 0000 0000 0000 0000 0000 1100 0000 0000
• or t0, t1, t2
• 0000 0000 0000 0000 0011 1101 0000 0000
• not/nor
• A NOR 0 NOT(A OR 0) NOT(A)
• nor t0, t1, t3
• 1111 1111 1111 1111 1100 0011 1111 1111

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Summary of Logical Operations
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Making Decisions

• Decision making instructions
• Alter the control flow
• i.e., change the next instruction to be
  executed
• MIPS conditional branch instructions
• beq register 1, register 2, L1 go to Ll if
  s0s1
• bne register 1, register 2, L1 go to Ll if
  s0 ? s1
• Example
• if (ij) h i j
• bne s0,s1,Label
• add s3,s0,s1
• Label ...?

57
Branch-if-less-than

• We have beq, bne, what about Branch-if-less-than
  ?
• New instruction slt t0,s1,s2
• if s1 lt s2 then t0 1
• else t0 0
• Can use this instruction to build blt s1, s2,
  Label can now build general control
  structures
• Note that the assembler needs a register to do
  this, there are policy of use conventions for
  registers

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Control

• MIPS unconditional branch instructions
• j Label
• jr s2 (jumps to address held in s2)
• Formats

J

op 26 bit address
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Conditional Branches

• Example
• if (ij) bne s3,s4,Else
• go to Else if i ? j
• fgh add s0,s1,s2
• f g h (skipped if i ? j)
• else j Exit
• go to Exit
• fg-h Else sub s0,s1,s2
• f g h (skipped if ij)
• Exit

Exit
60
Compiling a while Loop in C

• Ex. while ( savei k )
• i i j
• Loop add t1, s3, s3
• add t1, t1, t1
• add t1, t1, s6 t1 gets address of
  savei
• lw t0, 0(t1) t0 gets savei
• bne t0, s5, Exit go to Exit if
  condition is false
• add s3, s3, s4 i i j
• j Loop
• Exit

61
Review of Instructions

• Instruction add s1,s2,s3 sub s1,s2,s3 lw
  s1,100(s2) sw s1,100(s2) bne s4,s5,L
• beq s4,s5,L
• j Label
• Formats

• Meanings1 s2 s3s1 s2 s3s1
  Memorys2100 Memorys2100 s1Next
  instr. is at Label if s4 ? s5Next instr. is at
  Label if s4 s5
• Next instr. is at Label

R I J
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More Branch Instructions (1/2)

• The slt instruction Set On Less Than
• slt t0, s3, s4 if s3 lt s4 then t0
  1 else t0 0
• slt t0, s1, zero
• compares s1 to (register) zero
• slti t0, s2, 10 t0 1 if s2 lt 10
• slti slt immediate

63
More Branch Instructions (2/2)

• No branches on less than directly
• Because its too complicated
• Two faster instruction are more useful

• Can use slt, beq, bne, and the fixed value of 0
  in register zero to create other conditions
• less than blt s1, s2, Label
• less than or equal to ble s1, s2, Label
• greater than bgt s1, s2, Label
• great than or equal to bge s1, s2, Label

slt at, s1, s2 at set to 1 if bne at,
zero, Label s1 lt s2
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Case/Switch Statement

• Jump address table
• A table of address of alternative instruction
  sequences
• An array of words
• MIPS include a jump register (jr)
• Unconditional jump to the address specified in a
  register
• Program loads the appropriate entry from the jump
  table into a register
• Then jump to the proper address using a jump
  register
• Described in Section 2.7

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So far

• Arithmetic
• add, sub
• Data transfer
• lw, sw
• Logical
• and, or, nor, andi, ori, sll, srl
• Conditional branch
• beq, bne, slt, slti
• Unconditional jump
• j

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So Far We Learn- MIPS Operands
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So Far We Learn-MIPS Assembly Language
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So Far We Learn-MIPS Machine Language
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Supporting Procedures

• Registers play a major role in keeping track of
  information for function calls.
• Register conventions
• Return address ra
• Arguments a0, a1, a2, a3
• Return value v0, v1
• Local variables s0, s1, , s7
• Temporary variables t0, , t7,t8, t9
• The stack is also used more later.

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Instruction for Functions

• ... sum(a,b)... / a,bs0,s1 /int sum(int
  x, int y) return xy
• address1000 1004 1008 1012 1016
• 2000 2004

C
MIPS
In MIPS, all instructions are 4 bytes, and stored
in memory just like data. So here we show the
addresses of where the programs are stored.
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Instruction for Functions

• ... sum(a,b)... / a,bs0,s1 /int sum(int
  x, int y) return xy
• address1000 add a0,s0,zero x a1004
  add a1,s1,zero y b 1008 addi
  ra,zero,1016 ra10161012 j sum
  jump to sum1016 ...
• 2000 sum add v0,a0,a12004 jr ra
  new instruction

C
MIPS
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Instruction for Functions

• ... sum(a,b)... / a,bs0,s1 /int sum(int
  x, int y) return xy
• 2000 sum add v0,a0,a12004 jr ra new
  instruction

C

• Question Why use jr here? Why not simply use j?
• Answer sum might be called by many functions, so
  we cant return to a fixed place. The calling
  proc to sum must be able to say return here
  somehow.

MIPS
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Instruction for Functions

• Single instruction to jump and save return
  address jump and link (jal)
• Before1008 addi ra,zero,1016
  ra10161012 j sum goto sum
• After1008 jal sum ra1012, goto sum
• Why have a jal? Make the common case fast
  function calls are very common. Also, you dont
  have to know where the code is.
• loaded into memory with jal.

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Instruction for Functions

• Syntax for jal (jump and link) is same as for j
  (jump)
• jal label
• jal should really be called laj for link and
  jump
• Step 1 (link) Save address of next instruction
  into ra (Why next instruction? Why not current
  one?)
• Step 2 (jump) Jump to the given label

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Instruction for Functions

• Syntax for jr (jump register)
• jr register
• Instead of providing a label to jump to, the jr
  instruction provides a register which contains an
  address to jump to.
• Only useful if we know exact address to jump to.
• Very useful for function calls
• jal stores return address in register (ra)
• jr ra jumps back to that address

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Instruction for Functions
77
Instruction for Functions

• We need t0, t1, and s0 registers for calculate
  f (g h)-(i j)

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Instruction for Functions
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The Stack Pointer
80
Procedure Call
???
????
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Memory Allocation on the Stack fp and sp
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Memory Allocation on the Heap
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Policy of Use Conventions
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So Far We Learn
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MIPS Machine Language
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Loading, Storing Bytes

• In addition to word data transfers (lw, sw),
  MIPS has byte data transfers.
• load byte lb
• store byte sb
• load halfword lh
• store halfword sh
• same format as lw, sw

87
How about larger constants?
88
How about larger constants?

• We'd like to be able to load a 32 bit constant
  into a register
• Must use two instructions, new "load upper
  immediate" instruction lui t0,
  1010101010101010
• Then must get the lower order bits right,
  i.e., ori t0, t0, 1010101010101010

1010101010101010
0000000000000000
0000000000000000
1010101010101010
ori
89
Assembly Language vs. Machine Language

• Assembly provides convenient symbolic
  representation
• much easier than writing down numbers
• e.g., destination first
• Machine language is the underlying reality
• e.g., destination is no longer first
• Assembly can provide pseudo instructions
• e.g., move t0, t1 exists only in Assembly
• Would be implemented as add t0,t1,zero
• When considering performance you should count
  real instructions

90
Other Issues

• Discussed in your assembly language programming
  lab support for procedures linkers, loaders,
  memory layout stacks, frames, recursion manipula
  ting strings and pointers interrupts and
  exceptions system calls and conventions
• Some of these well talk more about later
• Well talk about compiler optimizations when we
  hit chapter 4.

91
Overview of MIPS

• Simple instructions all 32 bits wide
• Very structured, no unnecessary baggage
• Only three instruction formats
• Rely on compiler to achieve performance what
  are the compiler's goals?
• Help compiler where we can

op rs rt rd shamt funct
R I J
op rs rt 16 bit address
op 26 bit address
92
Addressing in Branches and Jumps

• J type, which consists of 6 bits for the
  operation field
• e.g.,
• j Loop go to label Loop
• or
• j 10000 go to location 10000
• J-type format

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93
Conditional branch instruction

• e.g,
• bne s0, s1, Exit go to Exit it s0 !
  s1
• I-type format
• Restriction
• No program could be bigger than 216, which is far
  too small to be a realistic option today
• Program Counter (PC) Register Branch address
• PC-relative addressing (PC?????)

93
94
Branch Far Away

• Given a branch
• beq s0, s1, L1 16-bit offset
• Offers a much greater branching distance
• Replace it by a pair of instructions
• bne s0, s1, L2
• j L1 26-bit offset
• L2

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Addresses in Branches and Jumps

• Instructions
• bne t4,t5,Label Next instruction is at Label
  if t4 ltgt t5
• beq t4,t5,Label Next instruction is at Label
  if t4 t5
• j Label Next instruction is at Label
• Formats
• Addresses are not 32 bits
• How do we handle this with load and store
  instructions?

op rs rt 16 bit address
I J
op 26 bit address
96
Addresses in Branches

• Instructions
• bne t4,t5,Label Next instruction is at Label if
  t4?t5
• beq t4,t5,Label Next instruction is at Label if
  t4t5
• Format
• Could specify a register (like lw and sw) and add
  it to address
• use Instruction Address Register (PC program
  counter)
• most branches are local (principle of locality)

op rs rt 16 bit address
I
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MIPS Addressing Mode
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MIPS Instruction Formats
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Translating and Starting a Program
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Dynamically Linked Libraries

• Traditional approach to linking libraries before
  the program is run
• Static approach is the fastest way to call
  libraries routines
• Disadvantages
• If a new version of library Is released, the
  statically linked program keeps using the old
  version
• Loads the whole library even if all of the
  library is not used when the program is run
• Dynamically linked libraries (DLLs)
• Not linked and loaded until program is run

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Starting a Java Program

• Traditional model of executing a program
• Emphasis is on fast execution time for a program
• Java was invented with a different set of goals
• Quickly run safely on any computer
• Even if it might slow execution time

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Starting a Java Program (1/2)

• Rather than compile to the assembly language of a
  target computer
• Java bytecode instruction set
• That are easy to interpret

Java program
Compiler
Class files (Java bytecode)
Java Library routines
Just in Time compiler (JIT)
Java Virtual Machine (JVM)
Compiled Java methods
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Starting a Java Program (2/2)

• Java Virtual Machine (JVM )
• http//java.com/zh_TW/download/installed.jsp
• A software interpreter, can execute Java bytecode
• Just In Time compilers (JIT)
• Improve execution speed
• Typically profile the running program to find
  where the hot methods
• Compile them into the native instruction set
• Compiled portion is saved for the next time the
  program is run
• So that can run faster each time it is run

107
108
How Compilers Optimize

• High-level optimizations involve loop
  transformations
• Can reduce loop overhead
• Improve memory access
• In loops that execute many iterations
• Traditionally controlled by a for statement
• The optimization of loop unrolling is useful
• Loop unrolling
• Taking a loop and replicating the body multiple
  times
• Reduces the loop overhead and provides
  opportunities for many other optimizations

108
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How Compilers Optimize
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MIPS (RISC) Design Principles

• Simplicity favors regularity
• fixed size instructions 32-bits
• Always requiring 3 register operands
• small number of instruction formats
• opcode always the first 6 bits
• Good design demands good compromises
• three instruction formats
• Smaller is faster
• limited instruction set
• limited number of registers in register file
• limited number of addressing modes
• Make the common case fast
• arithmetic operands from the register file
  (load-store machine)
• allow instructions to contain immediate operands

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Alternative Architectures

• Design alternative
• Provide more powerful operations
• Goal is to reduce number of instructions executed
• Danger is a slower cycle time and/or a higher
  CPI
• Lets look (briefly) at IA-32

• The path toward operation complexity is thus
  fraught with peril. To avoid these problems,
  designers have moved toward simpler instructions

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IA - 32

• 1978 The Intel 8086 is announced (16 bit
  architecture)
• 1980 The 8087 floating point coprocessor is
  added
• 1982 The 80286 increases address space to 24
  bits, instructions
• 1985 The 80386 extends to 32 bits, new
  addressing modes
• 1989-1995 The 80486, Pentium, Pentium Pro add a
  few instructions (mostly designed for higher
  performance)
• 1997 57 new MMX instructions are added,
  Pentium II
• 1999 The Pentium III added another 70
  instructions (SSE)
• 2001 Another 144 instructions (SSE2)
• 2003 AMD extends the architecture to increase
  address space to 64 bits, widens all registers to
  64 bits and other changes (AMD64)
• 2004 Intel capitulates and embraces AMD64 (calls
  it EM64T) and adds more media extensions

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IA-32 Overview

• Complexity
• Instructions from 1 to 17 bytes long
• one operand must act as both a source and
  destination
• one operand can come from memory
• complex addressing modes, e.g., base or scaled
  index with 8 or 32 bit displacement
• Saving grace
• the most frequently used instructions are not too
  difficult to build
• compilers avoid the portions of the architecture
  that are slow
• what the 80x86 lacks in style is made up in
  quantity, making it beautiful from the right
  perspective

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IA-32 Registers and Data Addressing

• Registers in the 32-bit subset that originated
  with 80386

115
IA-32 Register Restrictions

• Registers are not general purpose note the
  restrictions below

116
IA-32 Typical Instructions

• Four major types of integer instructions
• Data movement including move, push, pop
• Arithmetic and logical (destination register or
  memory)
• Control flow (use of condition codes / flags)
• String instructions, including string move and
  string compare

117
IA-32 instruction Formats

• Typical formats (notice the different lengths)

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Summary

• Instruction complexity is only one variable
• lower instruction count vs. higher CPI / lower
  clock rate
• Design Principles
• simplicity favors regularity
• smaller is faster
• good design demands compromise
• make the common case fast
• Instruction set architecture
• a very important abstraction indeed!