Interconnect Networks for Reconfigurable SingleChip DSPs: Circuits, Architectures and Applications

1
Interconnect Networks for Reconfigurable
Single-Chip DSPs Circuits, Architectures and
Applications

• Hui Zhang
• Prof. Jan Rabaey
• BWRC Retreat, June 16-17, 1999

2
Reconfigurable Heterogeneous Single-Chip DSP
System
Data-Flow Kernels
System Architecture Template
MEM
MEM
AddrG
AddrG
AddrG
AddrG
uProc
Mem
Mem
Reconfigurable Interconnect Network
MAC
Kernel 1 Dot Product
MAC
MUL
ALU
FPGA
Kernel N FIR
Dedicated hardware modules (Heterogeneous)
Key component Reconfigurable Interconnect Network
3
Concepts of Reconfigurable Interconnect Network
Connection
Reconfiguration (?T)
network
C5
C2
C4
C1
C3
P Connections
Time
t0
t1
t2
N Input Ports
M Output Ports
Configuration period T

• Per-task reconfiguration
• T 100 1000 cycles, ?T ltlt T
• Per-application reconfiguration

N, M 25 200
4
Impact of Interconnect Network Architectures On
Energy and Area
Energy Breakdown
43
3
3
43
3
50
Energy (PJ)

• Area breakdown has similar distribution
• Be more careful with more complex systems
• Crossbar energy/area cost ? N2 , where N is the
  number of modules.
• Module energy/area cost ? N

5
Proposed Interconnect Architecture Hierarchical
Hybrid Mesh

• Exploit locality and regularity
• Building hierarchy by clustering
• Intra-cluster mesh structure
• Inter-cluster larger-granularity mesh

• Parameters
• number of buses per channel
• location of cluster switchboxes
• switchbox design, switch size

6
Comparison of Interconnect Architectures
Module-to-Module Connection Cost
Benchmark Results
Multiple-Bus
Mesh
Energy (PJ)
Hierarchical Mesh
0
1
3
4
5
6
7
8
2
9
10
Manhattan Distance (mm)
7
Proposed New Interconnect Circuits
Symmetric Source-follow Driver and Level
Converter (SSDLC)
Asymmetric Source-follow Driver and Level
Converter (ADLC)
Capacitive-Coupled Level Converter (CCLC)
Level Converter with Low-Vt devices (LCLVD)
Level Converting Register (LCR)
The best one Pseudo-Differential Interconnect
(PDIFF)
8
Comparison of Interconnect Circuits
Quality Metrics Energy and Delay
Energy(PJ)
Delay(ns)
EnergyDelay (PJ ns)

12
3.0
25
2.6
2.6
2.5
2.4
2.4
2.1
15

12

5.3
5.2
7.0
2.7
6
6.3
4.6
2.4
2.4
1.9
LCR
LCR
LCR
ADLC
CCLC
CCLC
ADLC
PDIFF
PDIFF
CCLC
ADLC
CMOS
CMOS
PDIFF
LCLVD
LCLVD
CMOS
SSDLC
SSDLC
LCLVD
SSDLC
These are normalized numbers.
Vdd2.0 V, C
1 PF
L
9
ChallengeTo Reduce Reconfiguration Overhead

• Static reconfiguration techniques to reduce
  overhead
• Prefetching technique with dual-context
  configuration memories for each switch.
• Configuration cache containing frequently or
  recently used kernel mappings.
• Partial reconfiguration
• DMA processor
• Dynamic reconfiguration

AG
MEM
MAC
ALU
MPY
MPY
ALU
const
C2
AG
MEM
C2
Example LMS kernel
Dynamic Reconfiguration

• Dynamic configuration context switch using
  multiple-context configuration memories.
• Switch box as a dynamic data steering element,
  controlled by data control tokens

10
Single-Chip Solution in the Communication Domain
Byte/word oriented data path
Control part
Bit-oriented data path
MEM
Cordic
AddrG
Core processor with distributed FSMs
Reconfigurable Interconnect Network
FPGA
MAC
MUL
ALU

• Error correction
• Part of viterbi decoding
• Pulse shaping

• Equalization
• Multi-user detection
• Part of viterbi decoding

• Protocol control
• Reconfiguration
• etc.

• Universal Radio, Software Radio
• Diverse channel and traffic characteristics
  adaptive data rate variable protocols and QoS
• Fast Prototyping
• Fast Time-to-Market with comparable ASIC
  performances