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Title: Lecture%2012%20Finite%20State%20Machine%20Design

1
Lecture 12Finite State Machine Design
• Prith Banerjee
• ECE C03
• Spring 1998

2
Outline
• Review of sequential machine design
• Moore/Mealy Machines
• FSM Word Problems
• Finite string recognizer
• Traffic light controller
• READING Katz 8.1, 8.2, 8.4, 8.5, Dewey 9.1, 9.2

3
Concept of the State Machine
Computer Hardware Datapath Control
Qualifiers
Registers Combinational Functional Units
(e.g., ALU) Busses
FSM generating sequences of control
signals Instructs datapath what to do next
Control
"Puppeteer who pulls the strings"
Control
State
Control Signal Outputs
Qualifiers and Inputs
Datapath
"Puppet"
4
Example Odd Parity Checker
Assert output whenever input bit stream has odd
of 1's
Reset
Present State
Input
Next State
Output
Even
0
Even
0
Even
1
Odd
0
0
Even
Odd
0
Odd
1
0
Odd
1
Even
1
1
1
Symbolic State Transition Table
Odd
Output
Next State
Input
Present State
1
0
0
0
0
0
0
1
1
0
1
1
0
1
State Diagram
1
0
1
1
Encoded State Transition Table
5
Odd Parity Checker Design
Next State/Output Functions
NS PS xor PI OUT PS
Input
Output
T
Q
NS
Input
CLK
D
Q
PS/Output
Q
CLK
R
Q
R
\Reset
\Reset
T FF Implementation
D FF Implementation
Input
1
0
0
1
1
0
1
0
1
1
1
0
Clk
1
1
0
1
0
0
1
1
0
1
1
1
Output
Timing Behavior Input 1 0 0 1 1 0 1 0 1 1 1 0
6
Timing of State Machines
When are inputs sampled, next state computed,
outputs asserted?
State Time Time between clocking events
Clocking event causes state/outputs to
transition, based on inputs For set-up/hold
time considerations Inputs should be
stable before clocking event After
propagation delay, Next State entered, Outputs
are stable NOTE Asynchronous signals take
effect immediately Synchronous
signals take effect at the next clocking
event E.g., tri-state enable effective
immediately sync. counter clear
effective at next clock event
7
Timing of State Machine
Example Positive Edge Triggered Synchronous
System
On rising edge, inputs sampled outputs,
next state computed After propagation delay,
outputs and next state are
stable Immediate Outputs affect datapath
immediately could cause inputs from
datapath to change Delayed Outputs take
effect on next clock edge propagation
delays must exceed hold times
Clock
Inputs
Outputs
8
Communicating State Machines
One machine's output is another machine's input
X
FSM 2
FSM 1
Y
Y0
X0
Y0
X0
A
C
1
0
X1
Y1
X1
B
D
0
1
Y0,1
X0
Machines advance in lock step Initial
inputs/outputs X 0, Y 0
9
Basic Design Approach
1. Understand the statement of the
Specification 2. Obtain an abstract
specification of the FSM 3. Perform a state
mininimization 4. Perform state
assignment 5. Choose FF types to implement FSM
state register 6. Implement the FSM
1, 2 covered now 3, 4, 5 covered later 4, 5
generalized from the counter design procedure
10
Example Vending Machine FSM
General Machine Concept
deliver package of gum after 15 cents
deposited single coin slot for dimes,
nickels no change
Step 1. Understand the problem
Draw a picture!
N
Block Diagram
Coin
Vending
Gum
Open
D
Sensor
Machine
Release
FSM
Mechanism
Reset
Clk
11
Vending Machine Example
Step 2. Map into more suitable abstract
representation
Reset
S0
Tabulate typical input sequences
N
D
three nickels nickel, dime dime, nickel two
dimes two nickels, dime
S1
S2
D
N
D
N
Draw state diagram
S4
S6
S3
S5
Inputs N, D, reset Output open
open
open
open
N
D
S8
S7
open
open
12
Vending Machine Example
Step 3 State Minimization
Inputs
Reset
0
N
5
N
10
N, D
15
open
reuse states whenever possible
Symbolic State Table
13
Vending Machine Example
Step 4 State Encoding
Inputs
14
Vending Machine Example
Step 5. Choose FFs for implementation
D FF easiest to use
Q1
Q1
Q1
Q1 Q0
Q1 Q0
Q1 Q0
D N
D N
D N
0 1 1 0
0 0 1 1
0 0 1 0
1 0 1 1
0 0 1 0
0 1 1 1
N
N
N
X X X X
X X X X
X X X X
D
D
D
1 1 1 1
0 1 1 1
0 0 1 0
Q0
Q0
Q0
K-map for D0
K-map for D1
K-map for Open
D
D
Q
D1 Q1 D Q0 N D0 N Q0 Q0 N Q1 N
Q1 D OPEN Q1 Q0
CLK
Q
R
N
\reset
N
OPEN
D
Q
CLK
Q
8 Gates
N
R
\reset
D
15
Alternative State Machine Representations
Why State Diagrams Are Not Enough
Not flexible enough for describing very complex
finite state machines Not suitable for gradual
refinement of finite state machine Do not
obviously describe an algorithm that is, well
specified sequence of actions based on
input data algorithm sequencing data
manipulation separation of control
and data Gradual shift towards program-like
representations Algorithmic State
Machine (ASM) Notation Hardware
Description Languages (e.g., VHDL)
16
Alternative State Machine Representations
Algorithmic State Machine (ASM) Notation
Three Primitive Elements State Box
Decision Box Output Box
State
Entry Path
State Code

State Machine in one state block per state
time Single Entry Point Unambiguous Exit Path
for each combination of inputs Outputs
asserted high (.H) or low (.L) Immediate
(I) or delayed til next clock
State Box
State
Name
ASM
State
Output List
Block
T
F
Condition
Output
Condition
Box
Box
Conditional
Output List
Exits to
other ASM Blocks
17
ASM Notation
Condition Boxes
Ordering has no effect on final
outcome Equivalent ASM charts A exits to
B on (I0  I1) else exit to C
18
ASM Example Parity Checker
Input X, Output Z
Nothing in output list implies Z not asserted
Z asserted in State Odd
Symbolic State Table
Present State Even Even Odd Odd
Next State Even Odd Odd Even
Input F T F T
Output A A
Encoded State Table
Present State 0 0 1 1
Next State 0 1 1 0
Input 0 1 0 1
Output 0 0 1 1
Trace paths to derive state transition tables
19
ASM Chart Vending Machine
0
00
10
10
T
T
D
D
F
F
F
F
N
N
T
T
15
5
01
H.Open
F
T
N
Reset
F
T
F
T
0
D
20
Moore and Mealy Machine Design Procedure
Moore Machine Outputs are function solely of the
current state Outputs change synchronously
with state changes
Z
X
k
i
Combinational
Outputs
Inputs
Logic for
Outputs and
Next State
State
Feedback
State Register
Clock
State
Register
Mealy Machine Outputs depend on state AND
inputs Input change causes an immediate
output change Asynchronous signals
Comb.
X
Combinational
i
Logic for
Inputs
Logic for
Outputs
Next State
Z
(Flip-flop
k
Outputs
Inputs)
Clock
state
feedback
21
Equivalence of Moore and Mealy Machines
Moore Machine
N D Reset
(N D Reset)/0
Mealy Machine
Reset/0
Reset
0
0
0
Reset
Reset/0
N
N/0
5
5
D/0
N D/0
0
N
N/0
10
10
D/1
0
N D/0
ND
ND/1
15
15
1
Reset
Reset/1
Outputs are associated with State
Outputs are associated with Transitions
22
States vs Transitions
Mealy Machine typically has fewer states than
Moore Machine for same output sequence
0
0/0
0
0
0
Same I/O behavior Different of states
1/0
0/0
0
1
0
1
1
1/1
0
1
2
1
1
S0
00
S0
0
IN
IN
S1
01
S1
1
Equivalent ASM Charts
IN
IN
S2
10
H.OUT
H.OUT
IN
23
Analyze Behavior of Moore Machines
Reverse engineer the following
J
X
A
Q
Input X Output Z State A, B Z
C
X
\A
K
Q
R
\B
FFa
\Reset
Clk
J
X
Z
Q
C
X
\B
K
Q
R
\A
FFb
\Reset
Two Techniques for Reverse Engineering Ad
Hoc Try input combinations to derive transition
table Formal Derive transition by
analyzing the circuit
24
Behavior in response to input sequence 1 0 1 0 1
0
100
X
Clk
A
Z
\Reset
Partially Derived State Transition Table
25
Formal Reverse Engineering
Derive transition table from next state and
output combinational functions presented to
the flipflops!
Z B
Ka X B Kb X xor A
Ja X Jb X
FF excitation equations for J-K flipflop
A Ja A Ka A X A (X B)
A B Jb B Kb B X B (X A
X A) B
Next State K-Maps
A
State 00, Input 0 -gt State 00 State 01, Input 1
-gt State 01
B
26
Complete ASM Chart of Moore Machine
00
0
1
0
X
X
1
01
10
1
0
1
0
X
X
Note All Outputs Associated With State Boxes No
Separate Output Boxes Intrinsic in Moore
Machines
27
Behavior of Mealy Machines
Clk
X
A
B
D
Q
J
Q
DA
C
C
Q
K
Q
R
R
\Reset
\Reset
A
DA
X
B
B
Z
X
A
Input X, Output Z, State A, B
State register consists of D FF and J-K FF
28
Signal Trace of Input Sequence 101011
100
Note glitches in Z! Outputs valid at following
falling clock edge
X
Clk
A
B
Z
\Reset
Partially completed state transition table based
on the signal trace
29
Formal Reverse Engineering
A B (A X) A B B X B Jb
B Kb B (A xor X) B X B
A B  X A B X B X Z A X
B X
Missing Transitions and Outputs
State 01, Input 0 -gt State 01, Output 1 State 10,
Input 0 -gt State 00, Output 0 State 11, Input 1
-gt State 11, Output 1
A
B
Z
30
ASM Chart of Mealy Machine
S0 00, S1 01, S2 10, S3 11
10
00
0
1
X
X
1
0
01
1
0
1
X
X
0
NOTE Some Outputs in Output Boxes as well as
State Boxes This is intrinsic in Mealy Machine
implementation
31
Synchronous Mealy Machines
Clock
X
i
Z
k
Combinational
Inputs
Outputs
Logic for
Outputs and
Next State
state
State Register
Clock
feedback
latched state AND outputs avoids glitchy outputs!
32
Finite State Machine Word Problems
Mapping English Language Description to Formal
Specifications
Case Studies Finite String Pattern
Recognizer Traffic Light Controller
We will use state diagrams and ASM Charts
33
Finite String Pattern Recognizer
A finite string recognizer has one input (X) and
one output (Z). The output is asserted whenever
the input sequence 010 has been observed, as
long as the sequence 100 has never
been seen. Step 1. Understanding the problem
statement Sample input/output
behavior
X 00101010010 Z 00010101000 X
11011010010 Z 00000001000
34
Finite String Recognizer
Step 2. Draw State Diagrams/ASM Charts for the
strings that must be recognized.
I.e., 010 and 100.
Reset
S0
0
Moore State Diagram Reset signal places FSM in
S0
S4
S1
0
0
S2
S5
0
0
S3
S6
Loops in State
Outputs 1
1
0
35
Finite String Recognizer
Exit conditions from state S3 have recognized
010 if next input is 0 then have 0100!
if next input is 1 then have 0101 01
(state S2)
Reset
S0
0
S4
S1
0
0
S2
S5
0
0
S3
S6
1
0
36
Finite String Recognizer
Exit conditions from S1 recognizes strings of
form 0 (no 1 seen) loop back to S1 if
input is 0 Exit conditions from S4 recognizes
strings of form 1 (no 0 seen) loop back to
S4 if input is 1
Reset
S0
0
S4
S1
0
0
S2
S5
0
0
S3
S6
1
0
37
Finite String Recognizer
S2, S5 with incomplete transitions S2 01 If
next input is 1, then string could be prefix of
(01)1(00) S4 handles just this
case! S5 10 If next input is 1, then string
could be prefix of (10)1(0) S2
handles just this case!
Final State Diagram
38
Review of Design Process
Write down sample inputs and outputs to
understand specification Write down
sequences of states and transitions for the
missing transitions reuse states as much as
possible Verify I/O behavior of your state
diagram to insure it functions like the
specification
39
Traffic Light Controller
A busy highway is intersected by a little used
farmroad. Detectors C sense the presence of cars
waiting on the farmroad. With no car on
farmroad, light remain green in highway
direction. If vehicle on farmroad, highway
lights go from Green to Yellow to Red, allowing
the farmroad lights to become green. These stay
green only as long as a farmroad car is detected
but never longer than a set interval. When
these are met, farm lights transition from Green
green. Even if farmroad vehicles are waiting,
highway gets at least a set interval as
green. Assume you have an interval timer that
generates a short time pulse (TS) and a long time
pulse (TL) in response to a set (ST) signal.
TS is to be used for timing yellow lights and TL
for green lights.
40
Traffic Light Controller
C
HL
FL
Highway
Highway
FL
HL
C
41
Traffic Light Controller
Tabulation of Inputs and Outputs
Input Signal reset C TS TL Output Signal HG, HY,
HR FG, FY, FR ST
Description place FSM in initial state detect
vehicle on farmroad short time interval
expired long time interval expired Description as
sert green/yellow/red highway lights assert
green/yellow/red farmroad lights start timing a
short or long interval
Tabulation of Unique States Some light
configuration imply others
Description Highway green (farmroad red) Highway
State S0 S1 S2 S3
42
Traffic Light Controller
Refinement of ASM Chart
43
Traffic Light Controller
Determine Exit Conditions for S0 Car
waiting and Long Time Interval Expired- C  TL
0
0
TL
1
1
0
C
H.ST
1
H.ST
Equivalent ASM Chart Fragments
44
Traffic Light Controller
S1 to S2 Transition Set ST on exit from
S0 Stay in S1 until TS asserted
Similar situation for S3 to S4 transition
H.ST
0
1
TS
45
Traffic Light Controller
S2 Exit Condition no car waiting OR long time
interval expired
H.ST
0
0
1
TS
1
H.ST
H.ST
H.ST
0
1
0
TS
1
Complete ASM Chart for Traffic Light Controller
46
Traffic Light Controller
Compare with state diagram
TL C
Reset
S0 HG S1 HY S2 FG S3 FY
S0
TLC/ST
TS/ST
TS
S1
S3
TS
TS/ST
TL C/ST
S2
TL C
on paths and conditions for exiting a state
Exit conditions built up incrementally, later
combined into single Boolean
condition for exit Easier to understand
the design as an algorithm
47
Summary
• Review of sequential machine design
• Moore/Mealy Machines
• FSM Word Problems
• Finite string recognizer
• Traffic light controller
• NEXT LECTURE Finite State Machine Optimization
• READING Katz 9.1, 2.2.1, 9.2.2, Dewey 9.3