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Intel

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Intel's Low Power Technology. With High-K Dielectric. Balapradeep Gadamsetti. Why this is required? ... SiO2 is running out of atoms for further scaling but ... – PowerPoint PPT presentation

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Title: Intel


1
Intels Low Power Technology
  • With High-K Dielectric

Balapradeep Gadamsetti
2
Why this is required?
  • Continuation of Moores Law
  • Transistor scaling with increased performance and
    Reduced Power Consumption

3
Introduction
  • Silicon Industry is scaling SiO2 for the past 15
    years and still continuing.
  • SiO2 is running out of atoms for further scaling
    but still scaling continues.

4
What is a Transistor ?
  • A simple switch
  • - current flows from source
  • to drain when gate is at certain
  • voltage otherwise it doesnt flow
  • Gate dielectrics (SiO2) are only a few atomic
    layers thick at this thickness even being
    insulator current leaks through.
  • Now Leakage Power became an Issue !!

5
Seeking new materials to drive Moores Law
6
Replacing SiO2 a challenge?
  • Materials chosen for replacing SiO2 should be
    thicker (to reduce leakage power) but should have
    a high-K value.

What is High-K ?
A measure of how much charge a material can
hold. AIR is the reference with
K1. "High-k" materials, such as hafnium
dioxide (HfO2), zirconium dioxide (ZrO2) and
titanium dioxide (TiO2) inherently have a
dielectric constant or "k" above 3.9, the "k" of
silicon dioxide.
7
  • Dielectric reduces Leakage power

8
Problems with High-K
  • Threshold Voltage Pinning- high-K and Polysilicon
    gate are incompatible due to Fermi level pinning
    at the High-K and Polysilicon interface which
    causes high threshold voltages in transistors
  • Phonon scattering - High-K/ Polysilicon
    transistors exhibit severely degraded channel
    mobility due to the coupling of phonon modes in
    high-K to the inversion channel charge carriers.

Both the above problems limit the transistor
switching speed !!!
9
High-K and PolySi are Incompatible
10
Mobility degradation in High-k\PolySi
11
Phonon Scatterings
12
Solution- Metal Gates
  • Metal gate electrodes are able to decrease phonon
    scatterings and reduce the mobility degradation
    problem.

Challenges with Metal Gates
Requires metal gate electrodes with CORRECT
work functions on High-K for both nMOS and pMOS
transistors for high performance.
13
Work functions for nMOS and pMOS
14
Breakthroughs with Metal Gates
  • N-Type metal and P-Type metal with the CORRECT
    work functions on high-K have been engineered.
  • High-K\metal-gate stack achieves nMOS and pMOS
    channel mobility close to SiO2's.
  • High-K\metal-gate stack shows significantly lower
    gate leakage than SiO2.

15
High-Metal-gate reduces leakage
16
pMOS mobility graph
17
nMOS mobility graph
18
Conclusion
  • Intel achieved 20 percent improvement in
    transistor switching speed
  • Reduced transistor gate leakage by over 10 fold.
  • Integration of more than 400 million transistors
    for dual-core processors and more than 800
    million for quad-core in Intel 45nm high-k metal
    gate silicon technology.

19
References
  • http//www.intel.com/technology/silicon/high-k.htm
  • http//www.physorg.com/news80.html
  • http//www.eetimes.com/conf/iedm/showArticle.jhtml
    ?articleID18305166kc5012
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