Designing with Verilog

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Designing with Verilog

• EECS150 Spring 2007 Lab Lecture 2
• Young Lee
• Greg Gibeling

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Today

• Top-Down and Bottom-Up
• Partitioning Interfaces
• Behavioral vs. Structural Verilog
• Administrative Info
• Blocking and Non-Blocking
• Verilog and Hardware
• Lab 2
• Primitives

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Top-Down vs. Bottom-Up (1)

• Top-Down Design
• Start by defining the project
• Then break it down
• Starts here

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Top-Down vs. Bottom-Up (2)

• Top-Down Design
• Ends here

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Top-Down vs. Bottom-Up (3)

• Bottom-Up Testing
• Faster, Easier and Cheaper
• Test each little component thoroughly
• Allows you to easily replicate working components

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Partitioning Interfaces (1)

• Partitioning
• Break the large module up
• Decide what sub-modules make sense
• Partitioning is for your benefit
• It needs to make sense to you
• Each module should be
• A reasonable size
• Independently testable
• Successful partitioning allows easier
  collaboration on a large project

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Partitioning Interfaces (2)

• Interfaces
• How different partitions talk to one another
• A concise definition of signals and timing
• Timing is vital, do NOT omit it
• Must be clean
• Dont send useless signals across
• Bad partitioning might hinder this
• An interface is a contract
• Lets other people use/reuse your module

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Behavioral vs. Structural (1)

• Rule of thumb
• Behavioral doesnt have sub-components
• Structural has sub-components
• Instantiated Modules
• Instantiated Gates
• Instantiated Primitives
• Most modules are mixed
• Obviously this is the most flexible

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Behavioral vs. Structural (2)
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Behavioral vs. Structural (3)
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Administrative Info

• Lab Grading
• Get it in by the opening of the next lab
• Partial credit will be given for incomplete labs
• Card Key Access for All is coming soon!
• Start looking for partners!

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Blocking vs. Non-Blocking (1)
Verilog Fragment
Result
always _at_ (a) begin b a c b end
C B A A-----B-------C
B Old A C Old B
always _at_ (posedge Clock) begin b lt a c lt
b end
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Blocking vs. Non-Blocking (2)

• Use Non-Blocking for FlipFlop Inference
• posedge/negedge require Non-Blocking
• Else simulation and synthesis wont match

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Blocking vs. Non-Blocking (3)

• If you use blocking for FlipFlops

YOU WILL NOT GET WHAT YOU WANT!
always _at_ (posedge Clock) begin b a // b will
go away c b // c will be a FlipFlop end // b
isnt needed at all
always _at_ (posedge Clock) begin c b // c will
be a FlipFlop b a // b will be a FlipFlop end
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Blocking vs. Non-Blocking (4)
Race Conditions
file xyz.v module XYZ(A, B, Clock) input B,
Clock output A reg A always _at_ (posedge
Clock) A B endmodule
file abc.v module ABC(B, C, Clock) input C,
Clock output B reg B always _at_ (posedge
Clock) B C endmodule
THIS IS WRONG
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Blocking vs. Non-Blocking (5)
Race Conditions
file xyz.v module XYZ(A, B, Clock) input B,
Clock output A reg A always _at_ (posedge
Clock) A lt B endmodule
file abc.v module ABC(B, C, Clock) input C,
Clock output B reg B always _at_ (posedge
Clock) B lt C endmodule
THIS IS CORRECT
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Verilog and Hardware (1)
assign Sum A B
reg 10 Sum always _at_ (A or B) begin Sum A
B end
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Verilog and Hardware (2)
assign Out Select ? A B
reg 10 Out always _at_ (Select or A or B)
begin if (Select) Out A else Out B end
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Verilog and Hardware (3)
assign Out Sub ? (A-B) (AB)
reg 10 Out always _at_ (Sub or A or B) begin if
(Sub) Out A - B else Out A B end
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Verilog and Hardware (4)
reg 10 Out always _at_ (posedge Clock) begin if
(Reset) Out lt 2b00 else Out lt In end
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Lab 2 (1)

• Lab2Top
• Accumulator
• Stores sum of all inputs
• Written in behavioral verilog
• Same function as Lab1Circuit
• Peak Detector
• Stores largest of all inputs
• Written in structural verilog

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Lab 2 (2)
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Lab 2 (3)
Accumulator.v
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Lab 2 (4)
PeakDetector.v
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Primitives (1)
wire SIntermediate, SFinal, CPropagrate,
CGenerate xor xor1( SIntermediate, In, Out)
and and1( CGenerate, In, Out) xor xor2( SFinal,
SIntermediate, CIn) and and2( CPropagate, In,
CIn) or or1( COut, CGenerate, CPropagate) F
DCE FF( .Q( Out), .C( Clock), .CE( Enable
), .CLR( Reset), .D( SFinal))
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Primitives (2)
wire SIntermediate, SFinal, CPropagrate,
CGenerate xor xor1( SIntermediate, In, Out)
and and1( CGenerate, In, Out) xor xor2( SFinal,
SIntermediate, CIn) and and2( CPropagate, In,
CIn) or or1( COut, CGenerate, CPropagate) F
DCE FF( .Q( Out), .C( Clock), .CE( Enable
), .CLR( Reset), .D( SFinal))
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Primitives (3)
wire SIntermediate, SFinal, CPropagrate,
CGenerate xor xor1( SIntermediate, In, Out)
and and1( CGenerate, In, Out) xor xor2( SFinal,
SIntermediate, CIn) and and2( CPropagate, In,
CIn) or or1( COut, CGenerate, CPropagate) F
DCE FF( .Q( Out), .C( Clock), .CE( Enable
), .CLR( Reset), .D( SFinal))