Life is CMOS: Why Chase the Life After

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Life is CMOSWhy Chase the Life After?

• George Sery
• Shekhar Borkar
• Vivek De
• Intel Corporation

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Outline

• Integration, performance, and power
• Device technology scaling challenges
• Leakage and leakage control techniques
• Micro architecture directions
• Summary

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Transistors
1B transistor integration capability
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Frequency
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Performance
Applications will demand TIPS performance
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Power Dissipation
Unconstrained power could reach 1,000s of watts
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Outline

• Integration, performance, and power
• Device technology scaling challenges
• Leakage and leakage control techniques
• Micro architecture directions
• Summary

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Physical Gate Length Trend
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Facilitated by 248, 193, 157, EUV lithography
evolution
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Supply Voltage Scaling
2.5V
1.8V
1.5V
1.3V
1.1V
0.85V
0.7V
0.6V
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Delay Scaling Trends
1.45 Tera Hertz
0.85V
Vcc0.75V
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15nm NMOS Transistor
2.63 THz _at_ 0.8V
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Source/Drain Leakage (Ioff)
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Gate Leakage
40 DVgs ? 5X IG
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THz Transistor Architecture
High K gate
Fully Depleted Channel
Raised S/D

• Eliminates subsurface leakage
• Solves high resistance
• Minimizes gate leakage
• Eliminates floating body effect
• Minimizes soft error rates
• 50 lower junction capacitance that PD SOI

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Raised SD with Depleted Substrate
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High K Reduces Gate Leakage
1E1
1E0
TiO2
1E-1
HfO2
)
2
1E-2
Ta2O5
ZrO2
SiO2
1E-3
_at_1V (A/cm
1E-4
OX
1E-5
J
Al2O3
1E-6
1E-7
1E-8
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0.50
1.00
1.50
2.00
2.50
3.00
3.50
2
C
(
m
F/cm
)
ox
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High-K Gate Dielectric Formed Using Atomic Layer
Deposition
Step 4

• Sequential introduction of precursors ZrCl4(g),
  H2O(g)
• Surface reaction between substrate each
  precursor until saturation

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DST Outperforms PD SOI
Ideal

• DST achieves steeper sub-threshold slope and
  lower Ioff than both PD SOI and bulk Si
• Up to 100x lower leakage than partially
  depleted SOI

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Raised Source and Drain Reduces Parasitic
Resistances and Improves IDSAT
1.3V
Raised S/D
1.3V
No Raised S/D
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30 increase in drive current!
30 increase in drive current!
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DST Enables Future Voltage Scaling
DST
BULK CMOS
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Outline

• Integration, performance, and power
• Device technology scaling challenges
• Leakage and leakage control techniques
• Micro architecture directions
• Summary

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Leakage Power
Excessive sub-threshold leakage power
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Dual VT Design Technique
Leakage 3X smaller (Active Standby) No
performance loss
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Leakage Control
Stack Effect
Body Bias
Sleep Transistor
Vbp
Vdd
Ve
Logic Block
Equal Loading
Vbn
-Ve
2-10X reduction
2-1000X reduction
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Effectiveness of RBB
RBB less effective at shorter L and lower VT
A. Keshavarzi et. al., 1999 2001
International Symp. Low Power Electronics
Design (ISLPED)
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SD Leakage of Stacks
Stack leakage is 5-10X smaller
S. Narendra et. al., 2001 International Symp.
Low Power Electronics Design (ISLPED)
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Stack Forcing
Delay Penalty
Leakage Reduction
Equal Loading
Stack Forcing Vs Longer L
Circuit technique provides additional VTs
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Exploiting Natural Stacks
32-bit Kogge-Stone adder
Y. Ye et. al., 1998 Symp. VLSI Circuits
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Outline

• Integration, performance, and power
• Device technology scaling challenges
• Leakage and leakage control techniques
• Micro architecture directions
• Summary

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Performance Efficiency of mArch

• Implications (in the same technology)
• New microarchitecture 2-3X die area of the last
  uArch
• Provides 1.5-1.7X performance of the last uArch

We are on the wrong side of a Square Law
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Design EfficiencymArch
In the same process technology, compare Scalar ?
Super-scalar ? Dynamic ?
Netburst 2-3X Growth in area 1.4X Growth in
Integer Performance 1.7X Growth in Total
Performance 2-2.5X Growth in Power
Pollacks Rule in actionPower inefficiency
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Improve mArch Efficiency
Thermals Power Delivery designed for full HW
utilization
Single Thread
ST
Wait for Mem
Multi-Threading
Wait for Mem
MT1
Wait
MT2
MT3
Multi-threading improves performance without
impacting thermals power delivery
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Special-Purpose HW

• Special-purpose performance ? more MIPS/mm²
• SIMD integer and FP instructions in several ISAs
• Integration of other platform components, e.g.
  memory controller, graphics
• Special-purpose logic, programmable logic, and
  separately programmable engines

Improve power efficiency with Valued Performance
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Exploit MemoryLow PD

• Large on die caches provide
• Increased Data Bandwidth Reduced Latency
• Hence, higher performance for much lower power

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Summary

• CMOS scaling is alive and well
• Lower power, Terahertz operation, Scalable beyond
  65nm node
• Key enabling elements demonstrated
• Depleted Substrate Transistor with raised source
  drain
• High k gate, 15nm CMOS gate length
• Design, micro architecture approaches continue
  key enabling
• Significant focus on leakage and speed-power
  optimization techniques