Verification Methodology Based on Algorithmic State Machines and Cycle-Accurate Contract Specifications - PowerPoint PPT Presentation

Loading...

PPT – Verification Methodology Based on Algorithmic State Machines and Cycle-Accurate Contract Specifications PowerPoint presentation | free to download - id: 206ff1-ZDc1Z



Loading


The Adobe Flash plugin is needed to view this content

Get the plugin now

View by Category
About This Presentation
Title:

Verification Methodology Based on Algorithmic State Machines and Cycle-Accurate Contract Specifications

Description:

Input: architectural (behavioral) description in HDL (Verilog, VHDL) or system ... Namely, to provide this unique correspondence between the ASM flowchart and a ... – PowerPoint PPT presentation

Number of Views:31
Avg rating:3.0/5.0
Slides: 26
Provided by: fox109
Learn more at: http://ewdtest.com
Category:

less

Write a Comment
User Comments (0)
Transcript and Presenter's Notes

Title: Verification Methodology Based on Algorithmic State Machines and Cycle-Accurate Contract Specifications


1
Verification Methodology Based on Algorithmic
State Machines andCycle-Accurate Contract
Specifications
  • Sergey Frenkel1 and Alexander Kamkin2
  • 1Institute of Informatics Problems of the Russian
    Academy of Sciences
  • E-mail fsergei_at_mail.ru
  • 2Institute for System Programming of the Russian
    Academy of Sciences
  • E-mail kamkin_at_ispras.ru

2
Design Steps
  • Architectural and RTL Design
  • Input architectural (behavioral) description in
    HDL (Verilog, VHDL) or system-level language
    (SystemC, SystemVerilog)
  • Output RTL description of the design
  • data path (interconnection of adders,
    multipliers, etc.)
  • control logic (FSM model of a control unit)
  • Logic Synthesis
  • Input RTL description of the design
  • Output gate-level description of the design
  • Physical Design
  • Out of our consideration

3
General Scheme of Design Verification
4
Challenges of Design Verification
  • 50-80 of ASIC / IP / SoC design effort goes to
    verification, what has effects on Schedule, Cost,
    Quality
  • computational complexity of formal verification
    is prohibited for many real-life designs
  • simulation is slow, requires billions of vectors
    for large designs, and exhaustive simulation is
    infeasible
  • the verification tools and methods need to scale
    well, and be able to support efficient debugging,
    have to allow for ongoing changes in the
    specification and the design
  • the methodology must be flexible enough to permit
    new design features, such as soft error
    detection, including fault latency and
    self-healing analysis

5
Two Ways of Design Verification (RTL)
Verification Via Simulation
Formal Verification



6
Possible Combination of the Verification
Approaches
  • a mechanical combination of the verification
    techniques part of design is verified by
    simulation, while another by a formal method
  • by using of formal specification for simulation
    verification
  • by using a semi-formal specification

7
Total Design Cost Reducing
  • A work of a designer is resulted in two or three
    activities and human/equipment resources which
    have been spent for one of them should be kept
    back in another

8
Semi-Formal Verification
Informal Specification
Formal Specification
Formal Verification
Verification via Simulation
Verdict Pass or Fail
9
Cycle-Accurate Contract Specifications
Operations Contracts of stages
Contracts of operations
Operation Contracts of stages
Contract of operation
pre(A)
10
Idea of the Method
Operation A
Operation B
  • post(A, 2) ? post(B, 1)

Test Oracle
Time

1
2
3
11
Branching and Other Features
12
Algorithmic State Machine (ASM)
  • An Algorithmic State Machine (ASM) is the
    directed connected graph containing an initial
    vertex (Begin), a final vertex (End) and a finite
    set of operators and conditional vertices.
  • The operators and conditional vertices have only
    one input, the initial vertex has no input.
    Initial and operator vertices have only one
    output, a conditional vertex has two outputs
    marked by 1 and 0. A final vertex has no
    outputs. Each operator include some body in a
    pseudo-code, and its execution takes a clock of
    the target system time
  • The following are the major steps in the ASM
    methodology
  • Describe the target system algorithm by ASM
    chart (using a pseudo-code)
  • Design the data path based on the ASM chart
  • Design the control logic based on the detailed
    ASM chart

13
ASM Example
  • Let us an operator Yb be implemented. The
    sequence of the actions after Yb can be
    represented by ASM as following
  • The operator Y3 is executed after Yb when
    x1x4x31,Y1 is executed afterYb when x1x31, Y5
    is excuted after Yb when x1x4x31 or x11, that
    is
  • Yb? x1x4x3Y3 x1x4x'3Y5 x1x'4Y1 x'1Y5

14
System/Logic Design by Abelite(Prof. Samary
Baranov, Holon Institute of Technology, Israel)
ASM-description
I2
I1
In
FSM
FSM
Micro operations
Joint ASM Flow Chart
RTL (VHDL)
Design Tools (SYNOPSIS,CADENCE)
15
About ASM Formalities
  • A possibility to use some ASM-based formalized
    verification is due to some formal rules, used
    for ASM flowchart construction. Namely, to
    provide this unique correspondence between the
    ASM flowchart and a target data path and control
    unit it is enough that a synthesis algorithm
    would obey the following rules
  • State boxes should contain only register
    statements, control signals in parentheses
  • All operations within a state box should be
    concurrently executable in one clock cycle
  • If the operations in two consecutive state boxes
    can be executed in the same clock cycle, then
    these two state boxes can be combined into one
    state box
  • For each register-transfer statement, there must
    be a path between the source and destination
    registers
  • The description contains the ordering of
    microoperations, namely, each of rectangle take
    one clock for its execution

16
Suggested Design Verification Methodology
17
Design verification
methodology (contd.)
Formal Verification
Behavioral Description in a verification language
(SMV)
Temporal properties of the system to verify
RUN
18
Temporal logic (CTL)
  • Temporal logic expresses the ordering of events
    in time by means of operators that specify
    properties.
  • E existential path quantifier
  • A universal path quantifier
  • X next time
  • F eventually
  • G globally
  • U until

19
(No Transcript)
20
Verification via Model Checking
21
A Fragment of ASM Operation Hierarchical
Description
22
ASM-Specified Model Checking(3-bit counter)
  • a1 a10 1 y7y8y9y10y11y12 Micro
    Instructions
  • a2 a3 1 y2y3 Y1 y1
  • a3 a1 1 y4 Y2 y2 y3
  • a4 a2 1 y1 Y3 y4
  • a5 a4 1 y4 Y4 y5 y3
  • a6 a7 1 y4 Y5 y6 y3
  • a7 a8 1 y1 Y6 y7 y8
    y9 y10 y11 y12
  • a8 a5 1 y5y3
  • a9 a6 1 y6y3 Micro
    Operations
  • a10 a9 1 y1
  • y1
    v(vc_in)mod 2
  • y3
    c_outvc_in
  • y4
    c_inc_out
  • y5
    b1v
  • y6
    b0v
  • y7
    b00
  • y8
    b10
  • y9
    b20
  • y10
    c_in1

23
Model Checking (cont.)
Conditions of Natural Ordering of Counting SPEC
AG (((bit00)(bit11) (bit20))
-gtAX((bit01)(bit11)(bit20))) SPEC AG
(((bit00)(bit11) (bit20)) -gtAX((bit01)(bit1
1)(bit21)))
24
Conclusion
  • An approach, that is a combination of ASM-based
    and contract-based approaches to hardware
    designs semi-formal verification is introduced
  • The approach allows to unify benefits of both
    formal and simulation-based methods for complex
    digital hardware designs verification at early
    designing stages
  • Presently there are some examples of this
    approach application to verification tests
    designing for one of unit of MIPS64-compatible
    microprocessor
  • The approach allows to describe complex digital
    hardware with pipelining, interlocks, branching,
    etc.

25
Thank You!
About PowerShow.com