332:578 Deep Submicron VLSI Design Lecture 13 Dynamic FlipFlops, Latches, Clocking, and Time Borrowi

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332578 Deep SubmicronVLSI DesignLecture
13Dynamic Flip-Flops, Latches, Clocking, and
Time Borrowing
David Harris and Mike Bushnell Harvey Mudd
College and Rutgers University Spring 2005
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Outline

• Clocking and CMOS Latches
• Time Borrowing
• Two-Phase Clocking
• Summary

Material from CMOS VLSI Design, by Weste and
Harris, Addison-Wesley, 2005
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Terminology

• Tokens held by memory elements (flip-flops and
  latches)
• Flip-flops perform sequencing distinguish
  current token from previous token
• Add extra delay called sequencing overhead
• Static storage has feedback to retain output
  indefinitely
• Dynamic storage maintains value as C charge
  that leaks away if not refreshed

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Max-Delay Constraints

• Latch sequencing overhead reduces time for
  combinational logic to compute
• When comb. Logic delay too great, have setup time
  failure or max-delay failure
• Sample wrong value into flip-flop
• Fix by using faster logic or lengthening clock
  period

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Max-delay Constraint
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Constraints with 2-phase Latches
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Pulsed Latches

• Only one latch is in critical path
• If pulse narrower than tsetup, data must set up
  before pulse rises
• If pulse wide enough to hide setup time,
  sequencing overhead is just one latch delay
• Last expression is sequencing overhead

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Pulsed Latches
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Min-delay Constraints

• If hold time large and contamination delay small
• Data incorrectly goes through 2 successive
  elements on one clock edge, corrupting system
  state
• Race condition, hold time failure, or min-delay
  failure

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Min-delay Constraints
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Min-delay

• If flip-flop contamination delay gt hold time
• Can safely use back-to-back flip-flops
• Otherwise
• Must add delay between FFs (with buffer)
• Use special slow FFs
• Example Testing scan chain

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Min-delay

• By making tnonoverlap large enough, avoid hold
  time failure
• Hard to generate and distribute non-overlapping
  clocks at high speed
• Instead, use clock and its complement
• tnonoverlap 0
• Same contamination delay constraint between
  latches and flip-flops

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Min-delay Constraint
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Confusing

• Contamination delay constraint applies to
• Each logic phase for latch-based systems
• Entire cycle of logic for flip-flops
• Latches require 2 X contamination delay of
  flip-flops
• Note flip-flop has internal race between two
  latches

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Pulsed Latch Min-delay Constraints
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Time Borrowing

• In a flop-based system
• Data launches on one rising edge
• Must setup before next rising edge
• If it arrives late, system fails
• If it arrives early, time is wasted
• Flops have hard edges
• In a latch-based system
• Data can pass through latch while transparent
• Long cycle of logic can borrow time into next
• As long as each loop completes in one cycle

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Time Borrowing Example
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Time Borrowing

• Example
• Pipelined CPU ALU must complete operation and
  bypass result back to ALU for use by a dependent
  instruction
• Most critical paths are in self-bypass loops

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How Much Borrowing?
2-Phase Latches
Pulsed Latches
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Pulsed Latches

• Time borrowing benefits
• Intentional time borrowing designer can more
  easily balance logic between half-cycles and
  pipeline stages
• Shortens design time balancing is done during
  circuit design, rather than requiring
  microarchitecture changes
• Opportunistic time borrowing delays differ
  between stages in fabricated chip
• Process environmental variations timing model
  inaccuracies
• Slow cycles can average out some variation

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Methodology

• Experienced designers
• Forbid intentional time borrowing until chip
  approaches tapeout
• Otherwise, designers assume that their pipeline
  stage can borrow time from adjacent stages
• Many designers assume this paths become
  excessive
• Problem hidden until full chip timing analysis
  done
• Too late to redesign all those paths

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Clock Skew and Balanced Delay Clock Generator

• Custom Design get rid of clock buffer
• Problem Clock Skew
• Must carefully distribute global clock signals

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CVSL Style Static Register
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RAM Cell Latch

• Reduced noise margin

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Double-Edge Triggered Register
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Dynamic Single Clock Latches
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Dynamic Single Clock Latches

• Eliminate feedback inverter transmission gate
• Reduce transistors
• Store latched value on gate C
• Clock-to-Q delay very small
• Could be transparent
• Need sharp anti-phase clocks
• Use internal clock inverter

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Single-Phase Dynamic Latch Clocking

• DEC Alpha (a) clocking
• Must characterize race conditions of latch
  needs care
• For a, clock tr tf
• Worked when lt 0.8 nsec
• Failed when 0.8 nsec tr, tf 1.0 nsec

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Summary

• Flip-Flops
• Very easy to use, supported by all tools
• 2-Phase Transparent Latches
• Lots of skew tolerance and time borrowing
• Pulsed Latches
• Fast, some skew tolerance borrow, hold time
  risk
• CMOS Latches