Secondgeneration FE asic for ILC calorimeters

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Second-generation FE asicfor ILC calorimeters
EWHA Workshop on silicon sensor
Seoul Presented by Julien Fleury
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Introduction EUDET module

• The module are not foreseen to be fully equipped
  with detector
• The point is to validate feasability and
  industrialisation
• One layer for feasability and one tower for
  physics

DHCAL (RPCs)
AHCAL (Sci w SiPM)
ECAL (Si PIN diodes)
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Common DAQ

• Timing is the same for all detectors
• Number of channels involves embedded electronic
  for all detectors
• Outputting of data is done the same way for all
  detectors
• ? Back-end of very-front-end shall be common for
  all detectors

VFE Asic
FE electronic
Detector
Concentrator
BE of VFE
FE of VFE
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Time considerations
Time between two trains 200ms (5 Hz)
time
Time between two bunch crossing 337 ns
Train length 2820 bunch X (950 us)
analog detectors only
A/D conv.
DAQ
IDLE MODE
Acquisition
1ms (.5)
.5ms (.25)
.5ms (.25)
199ms (99)
99 duty cycle
1 duty cycle
5
Read out token ring
1 event
5 events
3 events
0 event
0 event
Chip 0
Chip 1
Chip 2
Chip 3
Chip 4
Data bus
A/D conv.
DAQ
IDLE MODE
Chip 0
Acquisition
Chip 1
A/D conv.
DAQ
IDLE MODE
IDLE
Acquisition
Chip 2
A/D conv.
IDLE MODE
IDLE
Acquisition
Chip 3
A/D conv.
IDLE MODE
IDLE
Acquisition
Chip 4
A/D conv.
IDLE MODE
IDLE
DAQ
Acquisition
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Crucial common features

• Common backend
• Power Pulsing
• Start in a few µs
• Self trigger
• Whole chip triggered when 1 channel triggers
• External trigger for pedestal measurement

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Chip presentation

• HaRD_ROC ? DHCAL (RPC or GEMs)
• Hadronic RPC Detector Read Out Chip
• SKIROC ? ECAL (Silicon PIN)
• Silicon Kalorimeter Integrated Read Out Chip
• SPIROC ? AHCAL (SiPM)
• Silicon PM Integrated Read Out Chip

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HARD_ROC presentation

• DHCAL read out
• RPC or GEMs detector
• 64 channel
• Embed new DAQ

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HaRDROC architecture

• Based on existing MAROC chip (ATLAS luminometry
  for MaPMT readout)
• Full power pulsing
• Digital memory Data saved during bunch train.
  Only one serial output
• Store all channels and BCID for every hit. Depth
  128 bits

Multiplexed Analog charge output
Variable Slow Shaper 20-100 ns

SH



Variable Gain Preamp.
trig1lt0gt
64 INPUTS
Bipolar Fast Shaper
OR

Latch

Vth1 -








trig1lt63gt
trig0lt0gt
Gain correction 646bits G0 to 4

Latch


Vth0 -

trig0lt63gt
1 OUTPUT Transfered to DAQ during Inter-bunch

2 discri thresholds (210 bits)
2 DACs 10 bits
-Vth1
trig1lt0gt
-Vth0

trig1lt63gt

24 bit counter BCID
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HARD_ROC Acquisition mode

• Store up to 128 events in RAM
• Stop acquisition when ram_full signal asserted
• Common collector bus for ram_full signal

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HARD_ROC Readout mode

• Token ring mechanism initiated by DAQ
• Possibility to bypass a chip by slow control
• One data line activated by each chip sequentially
• Readout rate few MHz to minimize power
  dissipation
• With 500 pF bus capacitance, power dissipation is
  10uW/chip
• iCdV/dt 1 mA gt 1 mW for up to 100 chips on
  bus
• Readout time max (ram full) 10kbit 1 µs 10
  ms/chip

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One HaRD_ROC event
Discris results 642 bit
BCID 24 bit
Chip ID - 8 bit
Time
Position
Energy
? 160 bits / chip event

• Depht is 128

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SKIROC presentation

• ECAL read out
• Silicon PIN detector
• 36 channels
• Compatible new DAQ

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Main features

• Designed for 55 mm² pads
• 36 channels (instead of 72 to reduce cost of
  prototype)
• Detector AC/DC coupled
• Auto-trigger
• MIP/noise ratio on trigger channel 16
• 2 gains / 12 bit ADC ? 2000 MIP
• Energy resolution 4.89 GeV _at_90 (cf JCB)
• MIP/noise ratio 11
• Power pulsing
• Programmable stage by stage
• Calibration injection capacitance
• Embedded bandgap for references
• Embedded DAC for trig threshold
• Compatible with physic proto DAQ
• Serial analogue output
• External force trigger
• Probe bus for debug
• 24 bits Bunch Crossing ID

Digital on FPGA for debug
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One channel
16
Digital
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Block scheme of SKIROC
Analog channel
Analog mem.
36-channel Wilkinson ADC
Event builder
Main Memory SRAM
Ch. 0
Analog channel
Analog mem.
Ch. 1
ECAL SLAB
Analog channel
Analog mem.
Ch. 35
24 bit counter
Time digital mem.
Bunch crossing
Com module
Memory pointer
Trigger control
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One SKIROC event
ADC result 7212 bit
Gain 721 bit
BCID 24 bit
Chip ID - 8 bit
Position
Energy
Time
? 968 bits / chip event

• Depht is 5 because of room on silicon

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SKIROC dedicated to measurement

• Not designed for test beam but pure prototype
• 250 probing point embedded
• 2 ADCs 36 channels(LPCC LAL as a backup)
• Dual DAC 10 bit
• Bandgap
• Digital on FPGA flexibility

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SPIROC presentation

• AHCAL read out
• Silicon PM detector
• XX channels
• Compatible new DAQ

MARCH07
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SPIROC AHCAL SiPM Chip

• Chip fully dedicated to SiPMs developped after
  ECAL chip
• Internal DAC for SiPM gain adjustment (5V range)
• Auto-trigger (fast shaper Discriminator)
• Internal TDC, 1 ns step
• Internal 12 bit ADC
• Power pulsing

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Measurements

• Of blocks embedded in
• HaRD_ROC
• SKIROC

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MAROC Efficiency curves
33 cm2
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MAROC2 Wilkinson ADC meas.
INL (ADC count) vs Vin
1.5
-1.5
Vref shaper
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Wilkinson Linearity error (simulation)
Error (lsb)
1
0
-1
-2
-3
Input (V)
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Ramp ADC layout (1 channel)
LVDS receiver
12 bits Gray counter
100 um
Analog part
12 bits output register
1700 um
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Conclusions

• Second generation calorimeter ASICS now being
  designed for EUDET module
• Power pulsing, Zero-suppress, Auto-trigger
• Common design for backend
• HArDROC for DHCAL Readout submitted sept 06
• SKIROC for ECAL Readout submitted nov 06
• SPIROC for AHCAL Readout to be submitted in mar
  07
• Complementarity on design measurement
• System aspects to progress in parallel
• Stitchable PCBs for large module
• Second generation DAQ
• Power supplies ! Mechanics, reliability
• Low power low cost essential target