A Simple Deserializer

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A Simple Deserializer

• Anuj K. Purwar
• December 5, 2005

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Requirements

• Take input data stream from the read out chip and
  put out full data words.
• Single line speed approx. 140 Mbps with upto 6
  lines maximum.
• Check for end of word and whether data or synch
  word.

3
Workings

• Serial stream converted to parallel using shift
  registers (two 12 bit shift registers for 2
  lines).
• A 4 bit counter counts each word and checks for
  end of word bit b0 1.
• And gates check for data/sync word by checking if
  b12, b13 00.

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RTL schematic for simple deserializer
counter and logic to check data/sync word and
integrity
2 shift registers
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Current status

• Works in full timing simulation.
• Code downloads successfully into the FPGA on a
  Xilinx Spartan 3 test board.
• Next step to do real readout and check outputs
  using Logic Analyzer.