14:332:331 Computer Architecture and Assembly Language Spring 2006 Week 11: Microprogramming

1
14332331Computer Architecture and Assembly
LanguageSpring 2006Week 11 Microprogramming

• Adapted from Dave Pattersons UCB CS152 slides
  and
• Mary Jane Irwins PSU CSE331 slides

2
Simplifying Control Design

• For an implementation of the full MIPS ISA
• instructions can take from 1 clock cycle to 20
  clock cycles
• resulting in finite state machines with hundreds
  to thousands of states with even more arcs (state
  sequences)
• Graphical representations become impossibly
  complex
• Instead, represent the set of control signals
  that are asserted during a state as a low-level
  control instruction to be executed by the
  datapath
• microinstructions
• Executing the microinstruction is equivalent to
  asserting the control signals specified by the
  microinstruction

3
Microprogramming

• Microinstruction has to specify
• what control signals should be asserted
• what microinstruction should be executed next
• Each microinstruction corresponds to one state in
  the FSM and is assigned a state number (or
  address)
• Sequential behavior increment the state
  (address) of the current microinstruction to get
  to the state (address) of the next
• Jump to the microinstruction that begins
  execution of the next MIPS instruction (state 0)
• Branch to a microinstruction based on control
  unit input using dispatch tables
• need one for microinstructions following state 1
• need another for microinstructions following
  state 2
• The set of microinstructions that define a MPS
  assembly language instruction (macroinstruction)
  is its microroutine

4
Defining a Microinstruction Format

• Format the fields of the microinstruction and
  the control signals that are affected by each
  field
• control signals specified by a field usually have
  functions that are related
• format is chosen to simplify the representation
  and to make it difficult to write inconsistent
  microinstructions
• i.e., that allow a given control signal be set to
  two different values
• Make each field of the microinstruction
  responsible for specifying a nonoverlapping set
  of control signals
• signals that are never asserted simultaneously
  may share the same field
• seven fields for our simple machine
• ALU control SRC1 SRC2 Register control
  Memory PCWrite control Sequencing

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Review Multicycle Data and Control Path
PCWriteCond
PCWrite
PCSource
ALUOp
IorD
Control FSM
MemRead
ALUSrcB
MemWrite
ALUSrcA
MemtoReg
RegWrite
IRWrite
RegDst
PC31-28
Instr31-26
Shift left 2
28
Instr25-0
2
0
1
Address
Memory
0
PC
Read Addr 1
0
A
Read Data 1
IR
Register File
1
zero
1
Read Addr 2
Read Data (Instr. or Data)
0
ALUout
ALU
Write Addr
Read Data 2
Write Data
1
B
0
Write Data
1
4
1
0
2
Sign Extend
Shift left 2
3
Instr15-0
ALU control
32
Instr5-0
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Review Multicycle RTL Summary
Step R-type R-type Mem Ref Branch Branch Branch Jump
Instr fetch IR MemoryPC PC PC 4 IR MemoryPC PC PC 4 IR MemoryPC PC PC 4 IR MemoryPC PC PC 4 IR MemoryPC PC PC 4 IR MemoryPC PC PC 4 IR MemoryPC PC PC 4
Decode A RegIR25-21B RegIR20-16ALUOut PC (sign-extend(IR15-0)ltlt 2) A RegIR25-21B RegIR20-16ALUOut PC (sign-extend(IR15-0)ltlt 2) A RegIR25-21B RegIR20-16ALUOut PC (sign-extend(IR15-0)ltlt 2) A RegIR25-21B RegIR20-16ALUOut PC (sign-extend(IR15-0)ltlt 2) A RegIR25-21B RegIR20-16ALUOut PC (sign-extend(IR15-0)ltlt 2) A RegIR25-21B RegIR20-16ALUOut PC (sign-extend(IR15-0)ltlt 2) A RegIR25-21B RegIR20-16ALUOut PC (sign-extend(IR15-0)ltlt 2)
Execute ALUOut A op B ALUOut A sign-extend (IR15-0) ALUOut A sign-extend (IR15-0) ALUOut A sign-extend (IR15-0) if (AB) PC ALUOut PC PC31-28 (IR25-0 ltlt 2) PC PC31-28 (IR25-0 ltlt 2)
Memory access RegIR15-11 ALUOut MDR MemoryALUOut orMemoryALUOut B MDR MemoryALUOut orMemoryALUOut B MDR MemoryALUOut orMemoryALUOut B
Write-back RegIR20-16 MDR RegIR20-16 MDR RegIR20-16 MDR
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Our Microinstruction Format
Field Value Signal setting Comments
ALU control Add ALUOp 00 Cause ALU to add
ALU control Subt ALUOp 01 Cause ALU to subtract (compare op for beq)
ALU control Func code ALUOp 10 Use IR function code to determine ALU control
SRC1 PC ALUSrcA 0 Use PC as top ALU input
SRC1 A ALUSrcA 1 Use reg A as top ALU input
SRC2 B ALUSrcB 00 Use reg B as bottom ALU input
SRC2 4 ALUSrcB 01 Use 4 as bottom ALU input
SRC2 Extend ALUSrcB 10 Use sign extension output as bottom ALU input
SRC2 Extshft ALUSrcB 11 Use shift-by-two output as bottom ALU input
Register control Read Read RegFile using rs and rt fields of IR as read addrs put data into A and B
Register control Write ALU RegWrite, RegDst 1, MemtoReg 0 Write RegFile using rd field of IR as write addr and ALUOut as write data
Register control Write MDR RegWrite, RegDst 0, MemtoReg 1 Write RegFile using rt field of IR as write addr and MDR as write data
8
Our Microinstruction Format, cont
Field Value Signal setting Comments
Memory Read PC MemRead, IorD 0,IRWrite Read memory using PC as addr write result into IR (and MDR)
Memory Read ALU MemRead, lorD 1 Read memory using ALUOut as addr write results into MDR
Memory Write ALU MemWrite, IorD 1 Write memory using ALUOut as addr and B as write data
PC write control ALU PCSource 00 PCWrite Write PC with output of ALU
PC write control ALUOut-cond PCSource 01, PCWriteCond If Zero output of ALU is true, write PC with the contents of ALUOut
PC write control Jump address PCSource 10, PCWrite Write PC with IR jump address after shift-by-two
Sequen-cing Seq AddrCtl 11 Choose next microinstruction sequentially
Sequen-cing Fetch AddrCtl 00 Jump to the first microinstruction (i.e., Fetch) to begin a new instruction
Sequen-cing Dispatch 1 AddrCtl 01 Branch using PLA_1
Sequen-cing Dispatch 2 AddrCtl 10 Branch using PLA_2
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Dispatch (Branch) Logic

• Dispatch operations are implemented using special
  logic (PLAs)

Microcode Dispatch PLA_1 Microcode Dispatch PLA_1 Microcode Dispatch PLA_1
Opcode field Opcode Value (Addr)
000000 R-format Rexec (6)
000010 jmp Jump (9)
000100 beq Beq (8)
100011 lw Maddr (2)
101011 sw Maddr (2)
Microcode Dispatch PLA_2 Microcode Dispatch PLA_2 Microcode Dispatch PLA_2
Opcode field Opcode Value (Addr)
100011 lw Memlw (3)
101011 sw Memsw (5)
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Creating the Microprogram

• Fetch microinstruction

Label (Addr) ALU control SRC1 SRC2 Reg control Memory PCWrite control Seqing
Fetch (0) Add PC 4 Read PC ALU Seq

• Label field represents the state (address) of the
  microinstruction
• Fetch microinstruction assigned state (address) 0

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Creating the Microprogram, cont

• Decode microinstruction

Label (Addr) ALU control SRC1 SRC2 Reg control Memory PCWrite control Seqing
Decode (1)

• Decode microinstruction assigned state (address) 1

12
Creating the Microprogram, cont

• Decode microinstruction

Label (Addr) ALU control SRC1 SRC2 Reg control Memory PCWrite control Seqing
Decode (1) Add PC Ext shft Read Disp 1

• Decode microinstruction assigned state (address) 1

13
Creating the Microprogram, cont

• Memory-reference (lw sw) microinstructions

Label (Addr) ALU control SRC1 SRC2 Reg control Memory PCWrite control Seqing
Maddr
Memlw
Memwb
Memsw

• Assigned states (addresses) 2, 3, 4, and 5

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Creating the Microprogram, cont

• Memory-reference (lw sw) microinstructions

Label (Addr) ALU control SRC1 SRC2 Reg control Memory PCWrite control Seqing
Maddr (2) Add A Extend Disp 2
Memlw (3) Read ALU Seq
Memwb (4) Write MDR Fetch
Memsw (5) Write ALU Fetch

• Assigned states (addresses) 2, 3, 4, and 5

15
Creating the Microprogram, cont

• R-type instruction microinstructions

Label (Addr) ALU control SRC1 SRC2 Reg control Memory PCWrite control Seqing
Rexec
Rwb

• Assigned states (addresses) 6 and 7

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Creating the Microprogram, cont

• R-type instruction microinstructions

Label (Addr) ALU control SRC1 SRC2 Reg control Memory PCWrite control Seqing
Rexec (6) Func code A B Seq
Rwb (7) Write ALU Fetch

• Assigned states (addresses) 6 and 7

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Creating the Microprogram, cont

• Branch (beq) and jump microinstructions

Label (Addr) ALU control SRC1 SRC2 Reg control Memory PCWrite control Seqing
Beq
Jump

• Assigned states (addresses) 8 and 9

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Creating the Microprogram, cont

• Branch (beq) and jump microinstructions

Label (Addr) ALU control SRC1 SRC2 Reg control Memory PCWrite control Seqing
Beq (8) Subt A B ALUOut-cond Fetch
Jump (9) Jump address Fetch

• Assigned states (addresses) 8 and 9

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The Entire Control Microprogram
Addr ALU control SRC1 SRC2 Reg control Memory PCWrite control Seqing
0 Add PC 4 Read PC ALU Seq
1 Add PC Ext shft Read Disp 1
2 Add A Extend Disp 2
3 Read ALU Seq
4 Write MDR Fetch
5 Write ALU Fetch
6 Func code A B Seq
7 Write ALU Fetch
8 Subt A B ALUOut-cond Fetch
9 Jump address Fetch
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Microprogram to Microcode

• A microassember is used to convert the mnemonic
  microprogram into the actual control signals (0s
  and 1) or microcode, for example

Label (Addr) ALU control SRC1 SRC2 Reg control Memory PCWrite control Seqing
Fetch (0) Add PC 4 Read PC ALU Seq
Label (Addr) ALU control SRC1 SRC2 Reg control Memory PCWrite control Seqing
ALUOp ALU SrcA ALU SrcB RegWrite, RegDst, MemtoReg MemRead, MemWrite, IRWrite, IorD PCSource, PCWrite, PCWriteCond AddrCtl
000 00 0 01 0,X,X 1,0,1,0 00, 1, X 11
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Microcode Implementation
PCWrite
PCWriteCond
IorD
MemRead
MemWrite
IRWrite
MemtoReg
Control PLA
Outputs
PCSource
ALUOp
ALUSourceB
ALUSourceA
RegWrite
RegDst
AddrCtl
1
Microprogram Counter
Adder
System clock
Addr select logic
sequencing control
Op0
Op1
Op2
Op3
Op4
Op5
Inst31-26
22
Address Select Logic
to control PLA
1
System Clock
Microprogram Counter
Adder
2
1
0
3
0
Dispatch PLA_2
Dispatch PLA_1
Addr select logic
Op0
Op1
Op2
Op3
Op4
Op5
Inst31-26
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Review FSM Implementation
PCWrite
PCWriteCond
IorD
MemRead
MemWrite
IRWrite
MemtoReg
Combinational control logic
PCSource
Outputs
ALUOp
ALUSourceB
ALUSourceA
RegWrite
RegDst
Inputs
Op0
Op1
Op2
Op3
Op4
Op5
Next State
State Reg
Inst31-26
System Clock
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Control Path Design Alternatives
Finite state diagram
Initial representation
Microprogram
Microprogram counter dispatch PLAs
Sequencing control
Explicit next state function
Logic representation
Logic equations
Microcode
Implementation technique
Programmable Logic Array (PLA)

• Microprogram representation advantages
• Easier to design, write, and debug