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## A Fast Algorithm for Power Grid Design

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### ... of Electrical and Computer Engineering. University of Minnesota ... Power supply network. Provides VDD and ground to time varying current sources (logic gates) ... – PowerPoint PPT presentation

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Title: A Fast Algorithm for Power Grid Design

1
A Fast Algorithm for Power Grid Design
• Jaskirat Singh
• Sachin Sapatnekar

Department of Electrical and Computer
Engineering University of
Minnesota
2
Introduction
• Power supply network
• Provides VDD and ground to time varying current
sources (logic gates)

VDD
• Power grid design issues
• VDD , wire width , currents
• IR drop/ground bounce
• Signal integrity
• Gate delay
• Electromigration
• Mean failure time for wires

GND
3
Introduction
• Power grid design problem
• Given an estimate of loading currents and power
pad positions
• Select a set of wire widths and pitches for the
multiple-layer network so that
• Wire area is efficiently utilized
• Nodes (branches) satisfy voltage drop (current
density) constraints
• Additional objectives of congestion
minimization/shielding

4
Introduction
Power grid design methods
5
Motivation
• Notion of locality in power grid design
• Fast Flip-chip Power Grid Analysis via Locality
and Grid Shell, Eli Chiprout, ICCAD04.
• To construct local grids focus on details of
local regions. Abstract far away regions of the
grid.

6
Locality Example
• 10 X 8 Grid
• Each branch 1 ohm
• Loaded with 1mA
• Vspec 0.9V

7
Locally Regular/Globally Irregular
• Globally regular grid
• Over design of the grid
• Globally irregular/locally regular grid
• Efficient use of wire area
• Reduced of optimizable parameters

8
Power Grid Design Procedure
Recursive bipartitioning heuristic based on
notion of locality
Abstraction of grids in partitions
Coarse grid representation initially
Post processing step to maximize wire alignment
9
Recursive Bipartitioning Method
• Divide and conquer approach
• Solve a local power grid design problem in each
step

k
2
2
4
1
3
3
5
K1
2
-1
10
Recursive Bipartitioning Method
Level-2 Partition
Level-1 Partition
Level-2 Partition
Level-k Partition
11
First level of partitioning
• Construct macromodels for the two partitions

12
First level of partitioning
• Stamp the macromodels in the global MNA system
• Solve each partition by hierarchical analysis
• For violations in a partition, fix it locally
• Speed up in circuit analysis step
• Use very thick wires for initial partition levels
• In subsequent partition levels refine the grid by
reducing the wire width

13
Second level of partitioning
• Use the power grid constructed at the first level
• Rip up the grid in left partition
• Add a horizontal partition wire
• Leave the grid in the right partition intact,
seen as an abstraction
• Construct a refined grid in the top-left and
bot-left partitions by the
• hierarchical design methodology

14
Second level of partitioning
?
• Requirements for power grid constructed in new
active partitions
• IR drop and EM constraints met in the active
partitions
• Maintain correctness of the power grid in the
right partition
• Solve new global system M Xb
• Compare old and new port voltages of the right
partition
• If Max( New_port_voltage Old_port_voltage) gt ?
(e.g., 1 VDD)
• ? Power grid in right partition is
disturbed
• ? Add more wires in the active partitions
and repeat the design procedure

15
Recursive bipartitioning algorithm
Make macro
Solve by hierarchical analysis
Detect violations
Decr pitch by ß
Check neighbor port voltages
Decr width by ?
Make next partitions
Done
Post processing to align wires
16
Recursive bipartitioning algorithm
• A breakdown scenario
• Min pitch violation
• Grid refinement doesnt work

Make_macromodels( ) Solve_grid( ) If(violations
in one or both partitions) Decr wire pitch of
violating partition
If (Pitch of the active partition lt min_pitch)
Min pitch violation
• Grids in neighboring partitions disturbed
• Cant be fixed by adding wires in active
partitions
• Traverse to the inactive partitions and add more
wires
• Adversely affects the runtime of the procedure
• Empirically a rare event if
• ? is 0.65,1 )

Check_neighbor_grids( ) If(port nodes of
neighbor grids perturbed) Decr wire pitch of
active partition
17
Post processing step
• At the end of design the wires might be
misaligned due to different wire pitches in
adjacent partitions
• Superimpose a uniform and continuous virtual grid
• Pitch of the virtual grid is chosen to be the
minimum pitch of all partitions
• Move the real power grid wires to the nearest
vacant position on the virtual grid
• Perform a complete simulation by hierarchical
analysis after the wire movements
• Add more wires if required on the virtual grid
place holders

18
Experimental Setup
• Input
• Floorplans with functional block current
estimates
• Power pad locations and number
• Grids constructed for power delivery to 2cm X 2cm
chip
• Vdd1.2V, Vspec1.08 V
• Sheet resistivity, current density, min pitch for
130nm tech
• Flip-chip (FC) ? 400-600 power pads
• Wire-bond(WB)?200-300 pads located at the
periphery
• Initial wire width 60-100 µm, k7 levels of
partitioning
• ? in (0.65,1 , ß in (0.5,1, ?15mv
• Output
• A non-uniform power grid that meets the IR drop
and EM constraints
• Wire width at the end of design is 2-6 µm

19
Experimental Results
• Power grids gt 1M nodes designed in 7-12 mins for
FC and 11-16 mins for WB
• Wire bond designs are suboptimal due to absence
of locality property

20
Experimental Results
• Proposed method compared with a previous work
• K. Wang and M. M Sadowska, On-chip Power
Supply Network Optimization using Multigrid-based
Technique, DAC04
• Multigrid method based on mapping from original
space to a reduced space

Multigrid Reduction
Optimization engine
Original mesh
Reduced mesh
Back mapping
21
Experimental Results
22
Experimental Results
• Constraints in the multigrid-based method
• All rows (columns) of wires are constrained to
have the same width
• Wastage of wiring resources

Current Densities
23
Experimental Results
Runtime comparison of the two power grid design
methods
Runtime is of the same order for the two methods
24
Summary
• A novel and efficient power grid design procedure
proposed
• Use notion of locality in grid design
• Accuracy is maintained by using circuit analysis
step in the inner loop
• Circuit analysis is made efficient by the use of
• Grid abstractions
• Coarse initial grid models followed by successive
grid refinements
• Considerably fast power grid design method with
efficient wire area utilization

25
• THANKS !!!
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