An Adaptive FPGA Architecture with Process Variation Compensation and Reduced Leakage

1
An Adaptive FPGA Architecture with Process
Variation Compensation andReduced Leakage

• Georges Nabaa
• Navid Azizi
• Pr. Farid Najm
• University of Toronto
• Actel Corporation

2
Outline

• Introduction
• Background on Threshold Voltage Variations
• Sources of Vth variations
• Impact of Vth on timing
• Impact of Vth on leakage
• Types of threshold variations
• FPGA Architecture Proposal
• Background on current architectures
• Proposed architecture goals
• High-Level Description
• Component-level Description
• Simulation goals and methodology
• Results
• Summary and Future Work

3
Introduction

• The threshold voltage is a fundamental
  operational parameter of a MOSFET
• For the past 30 years, performance improvements
  in semiconductors have been achieved by
  decreasing channel length
• This decrease had to be accompanied by a
• Decrease in supply voltage
• Decrease in threshold voltage (Vth)
• This Vth decrease has not been followed by a
  corresponding decrease in threshold voltage
  variations

4
Sources of Vth Variations

• Threshold Voltage variations are due to
  variations in
• Random dopants
• Channel Length
• Gate oxide Thickness

5
Random Dopant Fluctuations

• Threshold Voltage is a function of the dopants in
  the channel
• Due to the decrease in the number of dopants in
  DSM processes there is increased variability

• http//bwrc.eecs.berkeley.edu/classes/icdesign/ee2
  41_s06/Lectures/Lecture1-Intro.pdf

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Threshold Voltage Variations Impact Chip Timing
Yield

• Threshold voltage variations (dVth) cause
  variations in circuit delay that impact the
  chiptiming yield
• Can cause up to 30 variation in chip frequency
  BKN03
• The most critical paths may be different from
  chip to chip BKN03

Tschanz 2002
7
Threshold Voltage Variations Impact Chip Power
Yield

• Threshold voltage variations (dVth) cause
  variations in leakage that impact the chip yield
• 20x spread in subthreshold current for0.18 um
  (Tschanz 02)

Tschanz 2002
8
Types of Variations

• Threshold voltage variations can be divided into
• Die-to-die (inter-die)
• Within-die (intra-die)
• Die-to-die variations affect every element on a
  die equally
• Global
• Easier to account for and compensate
• Within-die variations produce non electrical
  uniformity for elements on the same chip
• Local
• Hard to account for and compensate

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Within-die variations

• Vth variations are known to have a DOMINANT
  within-die component below 150 nm
  Gyvez04Duval00
• The within-die component is expected to be
  proportionally larger as the feature length gets
  smaller
• Previously, simple solutions could be applied
• Chip-wide compensation schemes
• Binning
• Not enough when considering within-die variations
• Our proposed solution handles both die-to-die and
  within-die variations

10
Outline

• Introduction
• Background on Threshold Voltage Variations
• Sources of Vth variations
• Impact of Vth on timing
• Impact of Vth on leakage
• Types of threshold variations
• FPGA Architecture Proposal
• Background on current architectures
• Proposed architecture goals
• High-Level Description
• Component-level Description
• Simulation goals and methodology
• Results
• Summary and Future Work

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Background FPGA Architecture

• Field Programmable Gate Arrays (FPGAs) are
  Integrated Circuits (ICs) where
• the functions of the gates are programmable
• interconnections between, gates are programmable
• The programmable logic resources are calledlogic
  blocks
• The programmable interconnection resources are
  called routing blocks

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Background FPGA Architecture
13
Background FPGA Architecture

• Logic and routing blocks are configurable
  multiplexers.

Routing block
Logic block
Multiplexer
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Proposed Architecture Goals

• State of the Art FPGAs are manufactured in a 90
  nm process and suffer from threshold voltage
  variations
• Some of the transistors that make up the blocks
  will have
• Lower Vth
• Nominal Vth
• Higher Vth
• Goal adjust Vth of these transistors to minimize
  the variance.
• HOW?

• Low Vth
• Fast
• Leaky

• High Vth
• Slow device
• Not leaky

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Body-Biasing

• Recall that the threshold voltage is strongly
  dependent on the body voltage(Diagram from
  Sedra)

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Bidirectional Adaptive Body-Biasing

• Body biasing modifies the threshold voltage
• RBB Reverse Body Biasing
• Increase Vth (NMOS)
• Makes device slower
• Less leaky
• FBB Forward Body Biasing
• Reduces Vth (NMOS)
• Makes device faster

• Must RBB

• Must FBB

• Low Vth
• Fast
• Leaky

• High Vth
• Slow device
• Not leaky

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Outline

• Introduction
• Background on Threshold Voltage Variations
• Sources of Vth variations
• Impact of Vth on timing
• Impact of Vth on leakage
• Types of threshold variations
• FPGA Architecture Proposal
• Background on current architectures
• Proposed architecture goals
• High-Level Description
• Component-level Description
• Simulation goals and methodology
• Results
• Summary and Future Work

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High-level DescriptionIn a nutshell we propose

• To add a characterizer circuit in the
  architecture
• That enables classification blocks of transistors
  on each die into different categories such as
• Low Vth
• High Vth
• Nominal Vth
• Use bidirectional adaptive body-biasing to adjust
  Vth based on this classification to minimize
• Performance variability
• Leakage variability
• Allow the CAD tool to minimize Leakage by further
  slowing down areas that have timing slack

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Component-Level Description

• In order to implement this idea we need to
• Characterize the blocks of transistors by
  categories according to their Vth value
• Characterizer circuit
• Store the resulting tags
• Characterization bits
• Generate the bias based on the stored information
• Body-biasing circuitry

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Proposed Architecture
21
Outline

• Introduction
• Background on Threshold Voltage Variations
• Sources of Vth variations
• Impact of Vth on timing
• Impact of Vth on leakage
• Types of threshold variations
• FPGA Architecture Proposal
• Background on current architectures
• Proposed architecture goals
• High-Level Description
• Component-level Description
• Simulation goals and methodology
• Results
• Summary and Future Work

22
Characterizer
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Characterizer Operation

• The characterizer relies on the phase difference
  between two clocks to determine the Vth valueof
  a block
• A clock is sent to the block being characterized
  and looped back to the input of the phase
  detector
• The phase difference which represents the delay
  through that block is sampled

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Characterizer Operation

• This delay has two components
• d nominal delay
• dd delay variability
• If dd is
• Positive then the device is slow (FBB)
• Negative then the device is fast (RBB)
• Scalability due to the incremental nature of our
  algorithm, this method can be extended to all
  the blocks on the chip

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Characterizer Operation

• The characterization process quantizes the
  Gaussian distribution into levels
• Each block of transistors must have a level at
  the end of the characterization
• Trade-off must be made on the number of levels

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Component 2 Configuration bits

• The number of quantization levels depends on the
  number of configuration bits
• An encoding is required to populate the
  configuration bits
• 3 levels require 2 bits
• 7 levels require 3 bits

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Component 3Body-biasing Circuitry

• Responsible for applying the body-bias based
  onthe stored tags
• Result the specific chip is calibrated

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Recap
Characterization
Configuration Bits
Body-biasing
Calibrated
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Outline

• Introduction
• Background on Threshold Voltage Variations
• Sources of Vth variations
• Impact of Vth on timing
• Impact of Vth on leakage
• Types of threshold variations
• FPGA Architecture Proposal
• Background on current architectures
• Proposed architecture goals
• High-Level Description
• Component-level Description
• Simulation goals and methodology
• Results
• Summary and Future Work

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Simulation Goals

• Simulation Goals
• Benchmark proposed architecture against standard
  architecture under within-die and die-to-die Vth
  variations
• Measures used for benchmarking
• Resulting timing Variability
• Resulting leakage Variability

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Simulation Methodology

• Model and generate ?Vth
• Input ?Vth into the spice simulator and record
• timing and leakage variability
• Constitute results for the standard architecture
• Based on the recorded timing data, compute
  calibration biases and feed back into spice deck
• Re-simulate and record
• Timing and leakage variability
• These are the results for the proposed
  architectures

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Simulation Methodology
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Vth Variation Modeling

• We model Vth variations (dVth ) as normally
  distributed random variables (RVs)
• The 3s limits of the Normals are from the
  technology files
• Adjusted using the Law of Area (Horstmann99)
• The larger the transistors, the smaller the input
  Vth variations
• Assume that within the LUT the distributions are
  fully Positively Correlated Normals

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Methodology

• Assume Linearity between process and delay
• From each sweep, the sensitivity is recorded as

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Timing Variability Reduction(3 Levels)
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Leakage Variability Reduction(3 levels)
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Timing Variability Reduction(7 levels)
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Leakage Variability Reduction(7 levels)
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Leakage Power Optimization

• Our architecture allows for leakage optimization
• 75 of routing blocks can be slowed down by 50
  AN04
• Allow the CAD tool to override the characterizer
  to slow down parts of the chip that can be slowed
  down
• Current methods that perform such optimizations
  assume no process variations.
• This is incorrect since the estimated timing
  slack might not reflect the reality due to
  process variations
• Such assumptions can lead to timing failures on
  silicon

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Leakage Power Optimization

• Goals compare the additional leakage
  optimization proposed in the architecture
  against
• Standard architecture (base case)
• Dual threshold voltage process
• Methodology
• For a set of industrial design benchmarks using
  Actel ProAsic3s architecture
• Use Actels SmartTime to extract the worst-case
  slack for each logic cell
• Assuming our architecture and given the slacks,
  generate the new voltage compensation bump-ups
• Compute the leakage gains

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Leakage Reduction under same performance
conditions
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Limitations

• Area overhead configuration bits
• Depends on the granularity
• 1.08 for 2 extra configuration bits assuming
  logic block granularity in a commercial FPGA(8
  LUT, 4 inputs)
• Area overhead needed by the characterizeris
  minimal
• Area overhead required by the body-biasing
  circuitry. Depends on the granularity used
• Triple well-bias

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Summary

• Proposed a new FPGA architecture that
• Minimizes Vth variations
• Resulting delay variability is reduced by up to
  3.3X
• Maximizes yield (timing and power)
• Optimizes leakage
• 3X reduction in leakage without any effect on
  performance