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Quarterly%20Technical%20Report%20II

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Computer Science and Engineering Department. High Speed CMOS A/D Converter Circuit ... Full 6bit precision without missing code. Better working : 9bit low power ADC ... – PowerPoint PPT presentation

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Title: Quarterly%20Technical%20Report%20II


1
Quarterly Technical Report II for Pittsburgh
Digital Greenhouse
High Speed CMOS A/D Converter Circuit for Radio
Frequency Signal
Kyusun Choi
Computer Science and Engineering Department
The Pennsylvania State University
2
Summary of the Quarterly Report II(1)
  • Project goals for this quarter
  • First prototype chip test
  • Test report
  • Design second prototype chip
  • 6bit and 8bit design in 0.18 ?m

3
Summary of the Quarterly Report II(2)
  • Accomplished project milestones
  • Total 25 prototype chips are received
  • 6 ADCs are in each prototype chip
  • 6bit high speed ADC
  • 6bit low power ADC
  • 8bit high speed ADC
  • 8bit low power ADC
  • 9bit high speed ADC
  • 9bit low power ADC

4
Summary of the Quarterly Report II(3)
  • Accomplished project milestones
  • 2. All 25 prototype chips are working
  • 3. Initial test results for six ADCs

ADCs Precision ADC signal delay
6bit high speed 4 bits 3.799 ns
6bit low power 6 bits 21.404 ns
8bit high speed 5 bits 7.249 ns
8bit low power 7 bits 18.612 ns
9bit high speed 6 bits 27.762 ns
9bit low power 8 bits 83.595 ns
5
Summary of the Quarterly Report II(4)
  • Accomplished project milestones
  • LSBs Delta-W (from layout design)

ADCs ?LSB (mV) ?Whp (?m) ?Whn (?m) ?Wmp (?m) ?Wmn (?m) ?Wlp (?m) ?Wln (?m)
6bit high speed 14.52 0.190 0.094 0.330 0.172 0.244 0.118
6bit low power 17.16 0.376 0.192 1.714 0.866 0.730 0.366
8bit high speed 3.54 0.076 0.022 0.072 0.046 0.056 0.020
8bit low power 3.76 0.076 0.028 0.198 0.094 0.092 0.050
9bit high speed 1.86 0.106 0.014 0.094 0.048 0.044 0.054
9bit low power 2.09 0.028 0.020 0.214 0.104 0.062 0.042
6
Summary of the Quarterly Report II(5)
  • Accomplished project milestones
  • 4. Chip testing and parameter extraction
  • 5. Second prototype chip design in 0.18?m
    technology (on going)
  • Tape-out target date 8/5/2001
  • Vendor MOSIS with TSMC 0.18 um foundry
  • Expected prototype chip delivery date 10/25/2001

7
Summary of the Quarterly Report II(6)
  • Publications
  • Paper Published in WVLSI
  • A 1-GSPS CMOS Flash Analog-to-Digital
    Converter for System-on-Chip Applications (April
    2001)
  • Paper Accepted in ASIC/SOC
  • Future-Ready Ultrafast 8bit CMOS ADC for
    System-onChip Applications (September 2001)

8
Prototype Chip(1)
Prototype chip photo
9
Prototype Chip(2)
Chip die photo
10
Prototype Chip(3)
Chip die corner photo
11
Prototype Chip(4)
Output pad driver photo
12
Prototype Chip(5)
Prototype chip tester setup
13
Chip Test Results(1)
  • ADC Operation with 6bit low power ADC
  • 100 KHz triangle wave

14
Chip Test Results(2)
  • ADC Operation with 6bit low power ADC
  • 400 KHz sine wave

15
Chip Test Results(3)
  • ADC Operation with 6bit low power ADC
  • 1 MHz square wave

16
Chip Test Results(4)
  • Delay of pad and multiplexor
  • Pad and multiplexor circuit

17
Chip Test Results(5)
  • Delay of pad and multiplexor
  • Actual measurement (Tin to Tout)

18
Chip Test Results(6)
  • Delay of pad and multiplexor
  • Actual measurement (Tin to Tout)
  • Simulation results

ADCs R. delay F. delay Avg. delay
Chip 3 3.450 ns 2.850 ns 3.150 ns
Chip 6 3.475 ns 2.825 ns 3.150 ns
Chip 7 4.250 ns 2.875 ns 3.563 ns
Processes Mux delay Pad Mux delay
T14Y_LO_EPI 0.414 ns 1.144 ns
TSMC_TT 0.332 ns 0.864 ns
19
Chip Test Results(7)
  • ADC signal operation
  • Block diagram

20
Chip Test Results(8)
  • ADC signal operation (0 V to 2.5 V)
  • Actual measurement
    (nSec)

ADCs Chip 6 Chip 15 Chip 16
6bit high speed 3.924 3.924 3.549
6bit low power 21.662 21.562 20.987
8bit high speed 6.887 7.787 7.074
8bit low power 18.687 18.662 18.487
9bit high speed 21.612 21.712 21.962
9bit low power 84.162 82.062 84.562
21
Chip Test Results(9)
  • ADC signal operation (0 V to 2.5 V)
  • Simulation with T14Y_LO_EPI
    (nSec)

ADCs t_comp t_gb1 t_gb2 t_gen t_rom t_out
6bit high speed 0.352 0.595 0.724 1.854 2.216
6bit low power 2.183 2.596 2.784 4.857 5.250
8bit high speed 0.358 0.556 0.800 1.066 1.624 1.914
8bit low power 0.873 1.103 1.341 1.534 2.169 2.502
9bit high speed 0.696 0.938 1.216 1.566 2.687 3.075
9bit low power 2.264 2.569 2.846 3.198 4.193 4.454
22
Chip Test Results(10)
  • ADC signal operation (0 V to 2.5 V)
  • Simulation with TSMC_TT
    (nSec)

ADCs t_comp t_gb1 t_gb2 t_gen t_rom t_out
6bit high speed 0.287 0.488 0.587 1.570 1.850
6bit low power 1.972 2.322 2.482 4.205 4.506
8bit high speed 0.292 0.449 0.656 0.863 1.225 1.430
8bit low power 0.705 0.903 1.089 1.264 1.701 1.931
9bit high speed 0.579 0.781 1.014 1.287 2.055 2.330
9bit low power 2.066 2.319 2.551 2.823 3.491 3.740
23
Chip Test Results(11)
  • ADC signal operation (0.6 V to 1.7 V)
  • Actual measurement
    (nSec)

ADCs Chip 6 Chip 15 Chip 16
6bit high speed 6.912 5.562 3.512
6bit low power 38.911 37.861 38.861
8bit high speed 14.562 7.487 7.687
8bit low power 17.962 17.574 17.462
9bit high speed 31.862 31.211 34.212
9bit low power 108.862 106.862 109.762
24
Chip Test Results(12)
  • ADC signal operation (0.5 V to 1.76 V)
  • Simulation with T14Y_LO_EPI
    (nSec)

ADCs t_comp t_gb1 t_gb2 t_gen t_rom t_out
6bit high speed 0.614 0.876 1.060 2.017 2.383
6bit low power 3.179 3.682 3.872 7.808 8.186
8bit high speed 0.434 0.631 0.915 1.141 1.721 2.012
8bit low power 1.089 1.320 1.604 1.886 2.558 2.914
9bit high speed 1.089 1.320 1.573 1.917 3.060 3.483
9bit low power 3.446 3.793 4.067 4.415 5.404 5.775
25
Chip Test Results(13)
  • ADC signal operation (0.5 V to 1.76 V)
  • Simulation with TSMC_TT
    (nSec)

ADCs t_comp t_gb1 t_gb2 t_gen t_rom t_out
6bit high speed 0.540 0.755 0.899 1.734 2.011
6bit low power 2.500 2.909 3.064 6.202 6.481
8bit high speed 0.381 0.542 0.779 0.933 1.333 1.520
8bit low power 0.819 1.000 1.237 1.481 1.955 2.244
9bit high speed 0.819 1.000 1.237 1.505 2.302 2.629
9bit low power 2.701 3.001 3.236 3.509 4.183 4.437
26
Chip Test Results(14)
  • DNL and INL measurement
  • DNL with 6bit low power ADC - Chip 12

Chip DNL
6 0.49
12 0.27
27
Chip Test Results(15)
  • DNL and INL measurement
  • INL with 6bit low power ADC - Chip 12

Chip INL
6 1.19
12 1.20
28
Chip Test Results(16)
  • DNL and INL measurement
  • Simulation results
    (LSB)

ADCs T14Y_LO_EPI T14Y_LO_EPI TSMC_TT TSMC_TT
ADCs DNL INL DNL INL
6bit high speed 0.07 0.48 0.01 0.01
6bit low power 0.08 0.34 0.02 0.01
8bit high speed 0.09 1.96 0.04 0.03
8bit low power 1.18 1.21 0.17 0.10
9bit high speed 0.22 2.43 0.26 0.23
9bit low power 0.29 2.78 0.21 0.22
29
Chip Test Results(17)
  • Power consumption
  • Actual measurement
    (mWatt)

ADCs Sampling rate (msps) Avg. Power Max. Power
6bit high speed continuous 109.38 N/A
6bit low power continuous 35.25 N/A
8bit high speed continuous 170.50 N/A
8bit low power continuous 121.25 N/A
9bit high speed continuous 200.375 N/A
9bit low power continuous 179.625 N/A
30
Chip Test Results(18)
  • Power consumption
  • Simulation results
    (mWatt)

ADCs Sampling rate (msps) T14Y_LO_EPI T14Y_LO_EPI TSMC_TT TSMC_TT
ADCs Sampling rate (msps) Avg. Max. Avg. Max.
6bit high speed 1000 65.06 94.73 68.96 101.86
6bit low power 400 39.81 70.75 37.57 70.73
8bit high speed 667 238.43 330.80 254.76 353.78
8bit low power 500 171.81 255.78 165.29 254.87
9bit high speed 250 331.16 470.48 317.40 469.46
9bit low power 200 281.59 429.74 260.11 417.15
31
Chip Test Results(19)
  • Noise
  • Power supply noise

32
Chip Test Results(20)
  • Noise
  • Noise on ADC input pin

33
Chip Test Results(21)
  • Noise
  • Effects of noise to ADC output

34
Test Evaluation(1)
  • All 25 prototype chips are working
  • Best working 6bit low power ADC
  • Full 6bit precision without missing code
  • Better working 9bit low power ADC
  • 7bit operation without missing code
  • 8bit operation with few missing code
  • Other ADCs
  • Working but with lower precision
  • High speed ADC outputs show more noise and less
    precision

35
Test Evaluation(2)
  • Signal delay
  • 1. ADC design and simulation
  • TSMC_TT parameters
  • The wafer test result
  • T14Y_LO_EPI parameters
  • Re-simulation with T14Y_LO_EPI
  • 10 - 30 more signal delays
  • The actual measurements
  • at least 50 longer signal delays
  • Some possible reasons   

36
Test Evaluation(3)
  • Reduced precision
  • Process limitation
  • Layout dimension
  • LSBs ?W
  • On-chip power distribution
  • Separating analog power line
  • Noise on ADC input
  • High frequency noise appear on the ADC input
  • High frequency noise from power supply line   

37
Test Evaluation(4)
  • Others
  • Power consumption
  • Good match with simulation results
  • Overall 10-20 less than simulation
  • INL and DNL
  • INL and DNL are significantly increased
  • INL increase gt 1.0 bit LSB
  • DNL increase lt 0.4 bit LSB
  • Process variation on same wafer
  • Less than 3 variation
  • Overall consistent among the chips   

38
Test Evaluation(5)
  • Future testing to be done
  • DC specification test
  • Temperature drift effect
  • Power supply variation
  • AC specification test characterization
  • Signal-to-noise and distortion ratio
  • Effective number of bits
  • Signal-to-noise ratio
  • Total harmonic distortion
  • Spurious free dynamic range
  • Other dynamic performance

39
Second Prototype Chip Design(1)
  • 1. 0.18 ?m CMOS technology
  • 6bit, 8bit, and 9bit ADCs
  • Better precision
  • 2. New pad frame design
  • 3 sets of separate on-chip power supply
    distribution system
  • 84 pin package
  • 3. Limit LSBs Delta-W
  • ?W 0.1 ??m or 0.05 ?m

40
Second Prototype Chip Design(2)
  • 4. Sample and hold 2 stage pipeline
  • Adding sample and hold circuit
  • Adding digital pipeline registers
  • 5. Single inverter comparator
  • Test ADC with single inverter comparator
  • Determine high frequency operation limits
  • 6. ADC input shielding
  • Provide analog input shielding on chip

41
Conclusion
  • 1. Mission success for the first prototype chip
    fabrication
  • 6bit TIQ based ADC
  • Limits of TIQ based ADC
  • 2. Major mistakes on the first prototype chip
    design
  • 3. Expectation of second prototype chip
  • Full precision 6bit and 8bit ADCs on-chip
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