Thermal Analysis of a 3D FPGA for use in a PlaceandRoute algorithm'

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Thermal Analysis of a 3-D FPGA for use in a
Place-and-Route algorithm.

• Amir Hirsch and Vikram Chandrasekhar

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Overview

• Motivation
• Thermal Model
• Power Extraction
• Temperature Profiles
• Leakage
• Conclusions

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Why Model Temperature?
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Leakage vs Temperature
VT kT/q
HotLeakage A Temperature-Aware Model of
Subthreshold and Gate Leakage for Architects.
UNIV. OF VIRGINIA DEPT. OF COMPUTER SCIENCE TECH.
REPORT CS-2003-05
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3-D FPGA structure
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3-D FPGA switch matrix
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Need for a thermal model

• Tiles are much closer vertically than in a single
  layer
• Vertical thermal resistances much smaller than
  horizontal thermal resistances
• Important to understand how the temperature
  distribution in each layer, changes across layers

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Thermal Physics

• Heat Equation

C volumetric heat capacity (J / Km3) Specific
Heat mass density ? heat conductivity (W /
Km)Q heat generation density (W / m3)
Method 1. Discrete time and Discrete space. Use
MATLAB.Load thermal conductivity (K) from a GIF
layout file.Load heat generation density (Q)
from a GIF excitation file.
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Experimenting with the Model

• Wire in Insulator, thermally excited in center

Model
Excitation
After 10,000 iterations
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Experimenting with the Model

• Metal MIT in Insulator, Excited with varying heat

Model
Excitation
After 10,000 iterations
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Problems with Method 1

• Extraction of Q(x,y,z) is difficult
• Too slow to perform without a supercomputer
  (10,000 iterations of a 5000 node model took 2
  hours)

A material model of a layout provides for a
highly accurate simulation of but is impractical
to simulation entire 3-D layouts
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Lumped RC Model
We did not couple leakage into node power
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Benefits of this Model

• Extract the model to a SPICE simulation using
  thermal nodes as sub-circuits (speed is the SPICE
  simulators problem).
• We can only control the tile level layout in a
  place-and-route algorithm
• Useful for transient simulations

DC simulation is equivalent to solvingFast
matrix method for thermostatic equilibrium
inPlacement and Routing in 3D Integrated
Circuits, Univ. of Minnesota
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Switching power dissipation

• Fully-buffered switch architecture
• Bi-directional switches using tri-state buffers
• Every driver sees one input capacitance and one
  output capacitance for every switch

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Switching power in a tile

• Wires driven by tri-state buffers in a switch
  matrix
• Switching in input and output decoders
• Power dissipated in LUTs
• Each wire segment has its own switching activity
• Depends on current placement and routing of the
  circuit

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Computing switching activity

• Topologically sort the LUT network
• Assign random input probabilities to primary
  inputs
• Propagate the input probabilities across each
  level of LUTs till the primary outputs
• In every LUT, sum up probabilities of cells
  storing '1' being accessed
• Switching activity Probability of a net making
  a 0?1 transition

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Extraction from routing

• Switching activities need to be computed only
  once for a circuit
• Need to extract the following for every tile in
  the current routing
• Which are the nets routed through this tile ?
• What are their switching activities ?
• What is the total switching power dissipated in
  this tile ?

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Obtaining temperature profiles

• Get the relative switching power dissipated by
  the tiles
• Provides the node power for every node in the
  lumped thermal RC model
• The number of tiles used by the routing and the
  total switching power do not vary much
• But the temperature distribution depends on
  relative placement of high activity tiles

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Switching power distribution
Top layer of alu4 mapped to a 4 layer FPGA
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Switching power across layers
Layer 1 switching power
Layer 2 switching power
Layer 4 switching power
Layer 3 switching power
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Comparison of single and multiple layer FPGAs
Switching power for single layer FPGA
Switching power for top layer of four layer FPGA
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Temperature Profile
ALU4 mapped onto top layer only
Temperature across FPGA (Top Layer)
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Temperature Profile
ALU4 mapped to four layers
Top Layer Temperature
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Temperature Profile
ALU4 mapped to four layers
Top Layer Temperature
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Interlayer Gradient
Interlayer Temperature Gradient
Mean percentage temperature difference across
layers for ALU4 mapped to top layer
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Interlayer Gradient
Interlayer Temperature Gradient
Mean percentage temperature difference across
layers for ALU4 mapped to four layers
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Leakage
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ALU4 mapped to one layer. Layer 1 Leakage
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ALU4 mapped to one layer. Layer 2 Leakage (3,4
look same)
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Total Leakage on all four layers .0024
If unused cells do not leak 1.2857 x 10-4
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ALU4 mapped to four layers. Layer 1 Leakage
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ALU4 mapped to four layers. Layer 2 Leakage
Total Leakage on all four layers .0034
If unused cells do not leak 6.8338 x 10-4
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Conclusions

• Its useful to think about thermal issues using
  an equivalent lumped RC method
• Temperature differs little between layers so we
  stack high activity nodes to minimize the hotspot
  area this does not necessarily reduce leakage

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Use in a 3-D FPGA CAD tool

• Have to integrate the thermal model into the
  place-and-route tool
• Switching activity computation can be performed
  once for a circuit
• How should the switching activity be integrated
  into the cost functions ?
• Depends on the resulting temperature distributions

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Future work

• High activity tiles being placed far apart not
  necessarily a good solution
• Can even be a high-level option form multiple
  hot spots or a single hotspot
• Leakage power loopback to be done
• VDD scaling to be performed use of multiple
  layers reduces critical path delay
• Slow the circuit down by lowering VDD and observe
  the new temperature profiles