Compact%20Modeling%20for%20Symmetric%20and%20Asymmetric%20Double%20Gate%20MOSFETs - PowerPoint PPT Presentation

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Compact%20Modeling%20for%20Symmetric%20and%20Asymmetric%20Double%20Gate%20MOSFETs

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Long channel mobile charge and current models for asymmetric DG MOSFET. ... are very accurate (see WCM proceedings Vol. 3, pp. 849, June 1-5, (2008), Boston) ... – PowerPoint PPT presentation

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Title: Compact%20Modeling%20for%20Symmetric%20and%20Asymmetric%20Double%20Gate%20MOSFETs


1
Compact Modeling for Symmetric and Asymmetric
Double Gate MOSFETs
Henok Abebe The MOSIS Service USC Viterbi School
of Engineering Information Sciences
Institute Collaborators Ellis Cumberbatch and
Hedley Morris CGU School of Mathematical
Sciences, USA Vance Tyree USC/ISI
MOSIS, USA Shigeyasu Uno Nagoya
University, Department of Electrical and Computer
Engineering, Japan
1st International MOS-AK Meeting, co-located with
CMC Meeting and IEDM Conference, Dec.13 2008, San
Francisco, CA
2
Outline
  • 1-D symmetric undoped DG MOSFET modeling.
  • 2-D asymmetric and lightly doped DG MOSFET
    modeling.
  • Mid-section electrostatic potential
    approximation.
  • Long channel mobile charge and current models for
    asymmetric DG MOSFET.
  • Preliminary simulation results and comparison
    with numerical 2-D data.

3
1-D symmetric undoped DG MOSFET modeling
  • Undoped and symmetric.
  • Relatively small silicon thickness (eg. tsi5nm).
  • Two gate voltages are taken to be the same.
  • Thin gate oxide (eg. tox1.5nm).

4
Boundary conditions
1-D symmetric DG (continued)
  • Poisson equation


5
1-D symmetric DG (continued)
  • Exact solution using the first two boundary
    conditions
  • Surface potential

6
1-D symmetric DG (continued)
  • Interface boundary condition
    equation for ß

7
1-D symmetric DG (continued)
  • Total mobile charge per unit gate area
  • Channel current

8
Summary of the 1-D symmetric DG MOSFET
  • For charge and current calculations, equation
    needs solving at source and drain only.
  • Have efficient iteration algorithm to solve for
  • Results are very accurate (see WCM proceedings
    Vol. 3, pp. 849,  June 1-5, (2008), Boston)

9
2-D asymmetric and doped DG MOSFET modeling
Scaling
10
2-D asymmetric (continued)
Parabolic potential approximation
11
2-D asymmetric (continued)
Boundary conditions
12
2-D asymmetric (continued)
Surface potentials
Explicit solutions can be calculated for wsf and
wsb.
13
Mid-section electrostatic potential approximation
Long channel approximation
14
Mid-section (continued)
15
Long channel mobile charge and current models for
asymmetric DG MOSFET
Total mobile charge per unit gate area
Channel current
16
Preliminary simulation results and comparison
with numerical 2-D data
Mid-section potential versus relative gate
voltage and relative surface potential with 5nm
silicon thickness (lightly doped asymmetric DG
MOSFET)
17
Preliminary simulation (continued)
Mid-section potential versus relative gate
voltage and silicon thickness with 1.5nm oxide
thickness (lightly doped symmetric DG MOSFET)
18
Preliminary simulation (continued)
Channel current and output conductance versus
source-drain voltage with 5nm silicon and 1.5nm
oxide thicknesses (lightly doped symmetric DG
MOSFET)
19
Preliminary simulation (continued)
Channel current and tansconductance versus gate
voltage with 5nm silicon and 1.5nm oxide
thicknesses (lightly doped symmetric DG MOSFET)
20
Preliminary simulation (continued)
Channel current and output conductance versus
source-drain voltage with 5nm silicon and 1.5nm
oxide thicknesses (lightly doped symmetric DG
MOSFET)
21
Preliminary simulation (continued)
Channel current and tansconductance versus gate
voltage with 5nm silicon and 1.5nm oxide
thicknesses (lightly doped symmetric DG MOSFET)
22
Preliminary simulation (continued)
Channel current and output conductance versus
source-drain voltage with 5nm silicon and 1.5nm
oxide thicknesses (lightly doped symmetric DG
MOSFET)
23
Preliminary simulation (continued)
Channel current and tansconductance versus gate
voltage with 5nm silicon and 1.5nm oxide
thicknesses (lightly doped symmetric DG MOSFET)
24
University of Southern California (USC) Viterbi
School of Engineering Information Sciences
Institute (ISI) The MOSIS Service Marina del Rey,
California
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