Ankur Srivastava, Seda Ogrenci Memik, BoKyung Choi

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Achieving Design Closure Through Delay Relaxation
Parameter

• Ankur Srivastava, Seda Ogrenci Memik, Bo-Kyung
  Choi
• and Majid Sarrafzadeh
• University of Maryland, Northwestern University
  and UCLA

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Objectives

• Effective use of available design slack towards
  achieving design closure.
• Essentially we would like to increase the usable
  slack which could be used to improve any design
  objective and hence design closure
• Delay Relaxation Parameter is one such parameter
  that captures the notion of usable slack in RTL
  Designs

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Motivational Example
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Motivational Example
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Motivational Example
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Motivational Example
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Motivational Example

• Solution 1 Module 1 Op-1,5, Can Run in 2
  Cycles
• Module 2 Op-2,3,4,6,7,8 Run in 1 Cycle
• Solution 2 Module 1 Op-1,4,6,7,8 Run in 1 Cycle
• Module 2 Op-2,3,5 Run in 1 Cycle
• This Relaxed Delay/Latency Constraint Essentially
  could be used for Design Optimization

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Delay Relaxation Parameter DRP

• DRP Given an RTL design, Let Ci be the base case
  clock latency for a module, Let us suppose we can
  increase the latency for each module by Di
  without violating any of the schedule latency or
  resource constraint. Di is the DRP for module i
• Large amount of DRP can be exploited to optimize
  power, area, routability, fault tolerance and a
  wide spectrum of other cost functions
• DRP IS A GENERIC OBJECTIVE FUNCTION

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Contributions

• We propose DRP as a generic optimization
  objective during High Level Synthesis.
• We propose a post scheduling approach to
  optimizing DRP in RTL designs through effective
  budgeting and resource binding. The schedule
  latency, clock period and resource constraints
  are assumed as fixed.

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Optimizing DRP

• Optimizing DRP critically depends how well
  binding is done.
• Optimizing DRP also depends on how the latency of
  individual operations has been assigned.

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Optimizing DRP A 2 Step Approach

• Step 1 Delay Budgeting Given a scheduled DFG
  exploit the available operation slack and assign
  extra delays (latency) to operations such that
  the schedule latency and the resource constraints
  are unaffected. Since we do not perturb the
  schedule, the starting time of operations do not
  change.
• Step 2 Resource Binding Bind the resulted
  scheduled DFG into the given resources such that
  sum of all resource DRPs is maximized.

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Operation Budgeting

• Objective Assign additional latency/delay
  budgets to operations s.t. sum total of budget is
  maximized without violating schedule and resource
  constraints.

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Operation Budgeting
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• Theorem This Algorithm Gives the Optimal Value
  for Total Delay/Latency Budget

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Resource Binding

• The slowest that a functional module can be made
  to execute depends on the fastest operation bound
  on it. We would like to bind operations such that
  the total DRP in the RTL design is maximized.
• Basically we would like to bind operations with
  large latency since this would increase the DRP
  of that resource.

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Resource Binding

• Resource Binding is performed one clock step at a
  time.

Resource 1
Resource 2
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Input C/C/Fortran DFGs
Experimental Results
SUIF
Scheduling
Scheduling
Delay Budgeting
Synopsys BC
Power Driven Binding
DRP Driven Binding
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Experimental Results
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Conclusion and Future Work

• DRP was proposed as a generic optimization
  metric.
• Optimizing DRP improves the design quality in
  general and hence results in faster design
  closure
• Optimizing DRP by simultaneous scheduling/binding/
  budgeting would be an interesting course of
  future work.