MPtrees: A PackingBased Macro Placement Algorithm for MixedSize Designs

1
MP-trees A Packing-Based Macro Placement
Algorithm for Mixed-Size Designs

• Tung-Chieh Chen1, Ping-Hung Yuh1, Yao-Wen Chang1,
  Fwu-Juh Huang2, and Denny Liu2
• 1 National Taiwan University, Taipei, Taiwan
• 2 MediaTek Inc., Hsin-Chu, Taiwan
• DAC-2007
• Session 27.1

2
Outline

• Introduction
• Macro placement problem
• Multi-packing tree (MP-tree) representation
• Macro placement algorithm
• Experimental results
• Conclusions

3
Hard Macros Revolutionize SoC Design

• Enno Wein Jacques Benkoski, EEDesign, Aug 20,
  2004
• Hundreds of pre-designed macros
• Embedded memories, analog circuits, IP blocks
• Existing layout tools are having problems

600 500 400 300 200 100 0
80 70 60 50 40 30 20 10 0
Hard Macro
Standard Cell
2000 2001 2002 2003 2004 2005 2006
2000 2001 2002 2003 2004 2005 2006
of hard macros in SoC
Hard macro vs std-cell area ()
4
Previous Works

• Type 1 Simultaneous macro and cell placement
• Allow macro overlaps during the placement process
• Include APlace, Dragon, FengShui, Kraftwerk,
  mPL,FastPlace, NTUplace
• Need a robust legalizer
• Type 2 Constructive macro placement
• Keep macro overlap-free during the placement
  process
• Include Capo, PATOMA
• Type 3 Two-stage macro placement
• Consist of (1) macro placement and (2) cell
  placement
• Is robust in finding legal placement
• Is widely used in the industry
• Need a good macro placement

5
Outline

• Introduction
• Macro placement problem
• Multi-packing tree (MP-tree) representation
• Macro placement algorithm
• Experimental results
• Conclusions

6
Our Mixed-Size Placement Design Flow

• Based on the two-stage macro placement (type 3)

LEF/DEF In
Prototype
wirelength optimization
macro legalization (displacement
minimization, orientation optimization, congestion
optimization, etc.)
Target problem
Macro Placement
Standard Cell Placement
wirelength optimization, congestion optimization
DEF Out
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Macro Placement Problem

• Given
• A macro global placement
• Objective
• Remove all overlapsbetween macros
• Maximize continuous standard cell placement
  region
• Minimize macro movement (displacement)
• Approach
• Use floorplanning/packing techniques
• Place macros along thechip boundary

8
MP-tree Macro Placer

• Is based on binary trees
• Fast for operations and packing
• Has a structure that directly induces a special
  hierarchical framework to optimize the macro
  placement
• Subtrees local optimization
• Branch structure global optimization
• Handles various placement constraints
• Corner blocks, pre-placed blocks, placement
  blockages,and region constraints
• Can be integrated with state-of-the-art standard
  cell placers to obtain better mixed-size placement

9
Outline

• Introduction
• Macro placement problem
• Multi-packing tree (MP-tree) representation
• Macro placement algorithm
• Experimental results
• Conclusions

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Review B-Tree Floorplan Representation

• Chang et al., B-tree A new representation for
  non-slicing floorplans, DAC-2k.
• Given a B-tree, the legal floorplan can be
  obtained in amortized linear time.
• Left child the lowest, adjacent block on the
  right (xj xi wi).
• Right child the first block above, with the same
  x-coordinate (xj xi).

A compacted floorplan
The corresponding B-tree
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Problem of B-tree Packing
All macros are packed together
Desired solution
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Four Different Packing Directions
(Original B-tree definition)
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Handling Multiple Corners

• Divide the chip into different regions (NOT GOOD)
• Macro positions are over constrained.
• Assigning the regions for macros greatly affects
  the result.
• It may not obtain a desirable solution
• Need interactions among different regions.

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Multi-Packing Tree Representation

• Combine the packings of several packing trees
  todifferent corners
• Use the right skewed branch to integrate subtrees

branch node
branch edge
Level 1
packing subtree
Level 2
T1
Level 3
T2
T3
Level k
Tk1
Tk
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MP-tree Packing

• Depth-first order traversal
• Contours to compute y coordinates
• All BL-/BR-packing sub-trees use the
  bottom-contour
• All TL-/TR-packing sub-trees use the top-contour

contour
n0
n1
n3
n2
n7
n4
n5
n8
n6
BR-packing
n9
n10
BL-packing
TL-packing
n11
n12
TR-packing
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Outline

• Introduction
• Macro placement problem
• Multi-packing tree (MP-tree) representation
• Macro placement algorithm
• Flow
• Placement constraints
• Perturbation operations
• Placement evaluation
• Experimental results
• Conclusions

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Macro Placement Flow
simulated annealing loop
LEF/DEF in
Cluster macros
Perturb
Create a multi-packing tree (MP-tree)
Fix the tree structure
Optimize using simulated annealing
Pack
Evaluate the floorplan
Decluster macros
Accept/Reject
Post-Optimize
DEF out
Good enough
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Placement Constraints

• Corner macros
• Placement blockages preplaced macros
• Rectilinear macros
• Macro clustering and performance constraints
• Region constraints

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Corner Macros

• Constraint
• Fix some macros at the corner
• Solution
• Fix partial sub-trees

n1
n2
n3
b4
b1
n4
b3
b2
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Placement Blockages

• Constraint
• Avoid macros to overlap with blockages
• Solution
• Move macros along x/y direction during packing
• A pre-placed macro can also be treated as a
  placement blockage.

BL-Packing
n0
placement blockage
placement blockage
n1
n2
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Rectilinear Macros

• Constraint
• Handle rectilinear macros
• Solution
• Slice rectilinear macros into rectangular macros
• Adjust macros positions during packing

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Performance Constraints

• Constraint
• Abut some macros together
• Solution
• Cluster macros into a super macro
• Adjust super macro dimensions to find a desired
  solution

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Region Constraints

• Constraint
• Place macros in a desired region
• Solution
• Create sub-trees for region corners
• Optimize all sub-trees simultaneously

Create 12 sub-trees
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Operations on MP-tree

• Op1 Rotate a macro/cluster
• Op2 Resize a cluster
• Op3 Move a node in a packing tree to another
  place
• Op4 Swap two nodes within one or two packing
  subtrees
• Op5 Swap two packing subtrees

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Evaluation of a Macro Placement

• Macro placement area
• Macro displacement
• Wirelength
• Others

top contour
bottom contour
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Outline

• Introduction
• Macro placement problem
• Multi-packing tree (MP-tree) representation
• Macro placement algorithm
• Experimental results
• Exp1 Chip utilization
• Exp2 Integration with other placers
• Exp3 Mchip benchmark results
• Conclusions

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Experiment Setup

• Platform AMD Opteron 2.6GHz
• Benchmarks
• ISPD-06 benchmarks (8 circuits)
• Mchip benchmarks (5 circuits)
• Mixed-size placers
• NTUplace3 (NTU, ICCAD-06) (type 1)
• mPL6 (ULCA, ISPD-06) (type 1)
• Capo 10.2 (UMich, ISPD-06) (type 2)
• Experiments
• Exp1 Chip utilization (NTUplace3)
• Exp2 Integration with other placers (mPL6
  Capo)
• Exp3 Mchip benchmark results

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ISPD06 Placement Contest Benchmark Statistics

• Macros 9 to 68
• We choose macros that are 1000 times larger than
  average block size.
• Macro block area / total block area 15 to 83

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Exp1 Chip Utilization

• The average wirelength reduction increases when
  the chip utilization is higher.
• Util85 (improv. 1), Util90 (improv. 7), Util95
  (improv. 12)

w/o NTUplace3 alone MPT NTUplace3
MP-tree NR No legal results can be obtained.
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Exp1 ISPD-06 newblue3
NTUplace3 alone (failed to find a legal placement)
NTUplace3 MP-tree
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Exp2 Integration with Other Placers

• Capo 10.2 12 wire reduction, 21 more CPU time
• mPL6 4 wire reduction, more robust

NR No legal result can be obtained.
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Exp3 Mchip Benchmark Statistics

• Cell 540k to 1320k
• Macro 50 to 380
• Macro block area / total block area 30 to 66

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Exp3 Mchip Benchmark Results

• Placement HPWL is 35 shorter than Capos
• Routed WL is 55 shorter than Capos
• Compared to the leading commercial placers
• 6 -- 56 shorter HPWL
• 7 -- 67 shorter routed WL

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Mchip Benchmark Results
Mchip2
Mchip4
95 Macros
380 Macros w/ 4 region constraints
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Conclusions

• We proposed a macro placement algorithm based on
  the MP-tree representation
• MP-tree can handle various placement constraints.
• MP-tree is robust in finding legal macro
  placement and routable results.
• Integrating MP-tree with the state-of-the-art
  standard-cell placers, including NTUplace3, mPL6,
  and Capo, we can find legal mixed-size placement
  results with significantly better wirelength and
  routability.

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Thank You!